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ezheng
Level 1
Level 1
First reply posted First question asked Welcome!

Dear support and community member

Cypress S25FL256L-LAGMFM000

We've done a lot of test on this topic. While we are able to Erase (4K) with (0x20), Write (0x02), Read (0x48 or 0x03) security regions, we can't seem to make command 0x44 (Security Erase), or 0x42 (Security Write) working.

We are confident about SPI controller and the SPI master, since all other commands so far seems working perfectly. And as long as we change 0x44 to 0x20, 0x42 to 0x02, erase and write all work. But We don't want 4K erase.

Security Erase 0x44 command after sending SR1NV shows not WIP, so it is ready. And there is no error indicating in SR2V.

None of the security regions are locked, since we can do 4K erase, and program easily.

I can walkaround this issue by always doing 4K erase instead of 256-byte security erase for now. But we prefer to understand what is causing the trouble.

Please comment.

 

Thanks,

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1 Solution
AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Ezheng,

Thank you for contacting Cypress Semiconductor.

Before any command can be sent to the FLASH, please ensure that the Write Enable (WREN) command has been issued and decoded by the FLASH device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

In addition,  the Security Region is 1024 bytes so, the address bits for S25FL256L (A24 through A10) must be zero to initiate the Security Region Erase (SECRE 44h) command.
zero for this command. 

Please provide the Status Register and Configuration Register Settings on the S25FL256L.

Thank you in advance...

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

View solution in original post

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3 Replies
AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Ezheng,

Thank you for contacting Cypress Semiconductor.

Before any command can be sent to the FLASH, please ensure that the Write Enable (WREN) command has been issued and decoded by the FLASH device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

In addition,  the Security Region is 1024 bytes so, the address bits for S25FL256L (A24 through A10) must be zero to initiate the Security Region Erase (SECRE 44h) command.
zero for this command. 

Please provide the Status Register and Configuration Register Settings on the S25FL256L.

Thank you in advance...

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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ezheng
Level 1
Level 1
First reply posted First question asked Welcome!

Hi Albert, thanks for looking into this:

My sequence:

1. WREN (06h) sent, Read Status (05h) = 0x2 (this is WEL set)

2. Read Status 2 (07h) = 0x0 (no error)

3. Send Command 44h, 00h, 00h, 00h, 00h

4. Read Status (05h) = 0x3 then 0x0 (WIP active, then WEL is cleared by 44h command)

5. Read Status (07h) = 0x0 (no error)

Unfortunately, contents are not erased. Only change step-3 from 44h to 20h, then 4K of security region is erased. Same thing as of Security Region Program (42h), but Security Region Read (48h) works fine.

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AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Ezheng,

    < 2nd NOTICE >

Thank you for contacting Cypress Semiconductor.

Before any command can be sent to the FLASH, please ensure that the Write Enable (WREN) command has been issued and decoded by the FLASH device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

In addition,  the Security Region is 1024 bytes so, the address bits for S25FL256L (A24 through A10) must be zero to initiate the Security Region Erase (SECRE 44h) command.
zero for this command. 

Please provide the Status Register and Configuration Register Settings on the S25FL256L.

Thank you in advance...

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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