S25FL256L || How to put flash chip to Qaud QSPI mode

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abhishekps
Level 3
Level 3
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Hi Cypress Team,

I am trying to use S25FL256L flash chip with nordic controller in Quad QSPI mode.

How can I do that? I checked and it seems that configuring the CR1V register directly is the only way to achieve this which seems to be unsafe method. Maybe I missed something. Please help to clarify this.

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1 Solution

Hello,

 

Let me answer each of 5 points, although Andreas kindly helped to answer perfectly.

1. Yes, you can enable QSPI (1-4-4) mode by that sequence

 

2. The sequence described above does not touch the non-volatile register so it does not cause the register corruption.

 

3. The effect of the WRENV-WRR commands ends by power cycle or reset. That means you need to perform that sequence at every power-on.

 

4. No need to issue WRDI, but I agree with Andreas  about explicit WRDI before WRENV/WRR.

 

5. No, it won't be a problem.

 

Hopefully you have a clear understanding now and can proceed your project.

 

Thanks,

Takahiro

 

View solution in original post

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10 Replies
abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi,

We need this information urgently.

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Hello,

We are still reviewing and will get back to you.

Thank you

Regards,

Bushra

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andreas_bolsch
Level 1
Level 1
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What exactly do you mean by "Quad QSPI" mode? 1-1-4, 1-4-4 or 4-4-4 (instr., addr, data)? The last one, 4-4-4, is commenly referred to as QPI mode. This QPI mode is (de-) activated either by register write to CR2V or by the QPIEN(QPIEX commands. 

Why do you consider a register write as "unsafe"? If you want QUAD bit set by default at power-up use CR1NV. Applies to CR2V/CR2NV as well. 

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abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi Andreas,

I meant Quad 1-4-4 mode or 1-1-4 mode. Any of them will work for me.

I found that configuring this will involve WRR command and I checked one forum where it is mentioned that using WRR command and experiencing power cycle will corrupt the registers. Please find this link: https://community.infineon.com/t5/Knowledge-Base-Articles/Power-Loss-During-the-Write-Register-WRR-O....


Already few of our chips are not responding to Simple SPI commands.
So I just wanted to know that is there any other method available or this is the only way to do get in Quad 1-1-4 or 1-4-4.

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Well, of course power loss during any programming might cause corruption. But in the post you're referring to, a safe alternative is already mentioned: Only use the *volatile* configuration registers, and never touch the non-volatile ones. That's why I mentioned the pairs CR2V/CR2NV, same holds for CR1V/CR1NV.

Moreover, if the non-volatile registers are programmed only once at board manufacturing level, no problem would arise.

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It is mentioned there that using WRR command may cause corruption. And you are saying that writing on volatile is fine. So WRR command is not required while writing in volatile memory?

Currently my understanding was that I needed to follow below sequence:

  • WREN/WRENV
  • WRR
  • SR
  • CR1
  • CR2
  • CR3

 

Are you saying above is not necessary and below sequence should also work?

  • WRENV
  • SR
  • CR1
  • CR2
  • CR3

 

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andreas_bolsch
Level 1
Level 1
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Yes, the non-volatile ones just give the power-on values for the volatile registes. Even if corrupted, the volatile ones will revert to safe values from the non-volatiles after next power-cycle. 

The non-volatile ones are most likely flash based with automatic an erase-write-cycle. If there's a power glitch during this cycle ...

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abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi Andreas,

Let me confirm few more things with you:

  1. Is the below mentioned sequence correct for configuring in Quad QSPI mode (1-4-4)?
    a) WRENV
    b) WRR
    c) SR = SR
    d) CR1 = (CR1 & 0x02)
    e) CR2 = CR2
    f) CR3 = CR3

  2. Following above mentioned sequence will not result in permanent corruption of registers, everything will be fine after a reboot.
  3. Does the effect of command WRR(0x01) end after writing to the registers? Or its effect remains till we do a power reset? Or its effect lasts till we run write disable command (0x04)?
  4. Is adding Write Disable command (0x04) helpful in any way?
  5. If we are doing configurations using above sequence and after that performing erase and write operation which requires write enable command (0x06). Will it be a potential problem for us? This query is in reference to what is asked in 3rd point.

Please help to share answer for above queries. I believe complete understanding of these commands will help us while writing code.

 

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Stop! WRE*N*V followed by WRR and the desired register contents won't touch the non-volatile register but only update the volatile registers. These setting will persist until next power-on  or software reset (then the settings will revert to the contents of the non-volatile registers) or a new WRENV/WRR command sequence.

"The WRENV command will not set the Write Enable Latch (WEL) bit, WRENV is used only to
direct the following WRR command to change the volatile status and configuration register bit values." This means the WRENV only affects *one* following WRR command, but no other write or erase command. I.e. there is no need to issue a WRDI *afterwards*.

However, it might be a good idea to issue an explicit  WRDI *before* WRENV/WRR sequence in case the Write Enable latch was accidentally set.

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Hello,

 

Let me answer each of 5 points, although Andreas kindly helped to answer perfectly.

1. Yes, you can enable QSPI (1-4-4) mode by that sequence

 

2. The sequence described above does not touch the non-volatile register so it does not cause the register corruption.

 

3. The effect of the WRENV-WRR commands ends by power cycle or reset. That means you need to perform that sequence at every power-on.

 

4. No need to issue WRDI, but I agree with Andreas  about explicit WRDI before WRENV/WRR.

 

5. No, it won't be a problem.

 

Hopefully you have a clear understanding now and can proceed your project.

 

Thanks,

Takahiro

 

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