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abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi Cypress Team,

We are using S25FL256L chip in Quad QSPI Mode(1-4-4). 

I performed erase operation on flash using (0xD8) command after which I tried to read 1, 2, 3, 5, 10, 15 bytes of data one by one using command (0xEB). Read Source address location: 0x000000.

The output on each of these mentioned number of bytes is different and not correct.

1 byte: I am getting 0x00.

2 Byte: I am getting 0x00 0x00.

3 Byte: I am getting 0x88 0x88.

5 Byte: I am getting 0x88 0x88 0xff 0xff 0x00.

10 Byte: I am getting 0x88 0x88 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00.

15 Byte: I am getting 0x88 0x88 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0x00.

 

Please suggest what I am doing wrong here? I will also attach 1 waveform here of Clock with I/O0 for 5 byte read operation.

efd8d22c-4908-43eb-9c95-29bbb024bcac.jpg

 

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1 Solution
AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi @abhishekps 

Yes I am sending address along with D8h command. I am using erase API provided by Nordic SDK so I will have to recheck this. Is this command supposed to run in Single SPI mode when I am trying to use read and write in Quad QSPI? Yes, the D8h command and the address for erasing should be sent in Single SPI mode. There is no Quad erase command. 

In the sequence of commands mentioned, I don't see any step for polling the WIP bit in Status Register. Are you aware of the polling requirement? Please see datasheet section "8.6.3 Block Erase (BE D8h or 4BE DCh)". The WIP bit implies the status of any embedded operations being performed on the flash. When a program/erase operation is initiated, the WIP bit gets set to 1 indicating that the program/erase operation is in progress. We need to keep polling (reading the SR) the WIP bit to check its value. When the WIP bit becomes 0, it indicates that the operation was successfully complete. Along with the WIP bit, it is also recommended to read the error bits (P_ERR and E_ERR). These bits get set in case an error happens while program/erase. In case of error, WIP bit also remains stuck at 1.

Please confirm whether you are polling the WIP and E_ERR bits after initiating erase operation or not? If not, kindly include the step in your code.

In case you are facing difficulty with third party SDK, I would also like to inform you about the Low Level Driver for Serial Flash from Infineon. You can download the sLLD from this link. A sample project that shows interfacing S25FL064L with PSoC 6 can be found on this link

Please let me know if you have any further questions. 

Regards.

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3 Replies
AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi @abhishekps 

Could you please answer my below questions - 

  1. Could you please confirm that Quad mode has been enabled on the device successfully? Quad mode can be enabled by setting the QUAD_NV bit in CR1 NV register. It can also be enabled by setting the QUAD bit in CR1, however, please note that QUAD bit is volatile and after power cycle it will revert back to its default state (equal to QUAD_NV bit).
  2. Please note that the D8h command expects the command and address bits to be sent in on SI/IO0 line. Could you please confirm that you are using Single SPI for D8h command?
  3. How many devices are showing this behavior?
  4. Please note that even when Quad mode is enabled on a flash chip, the device still responds if commands are sent in Single SPI mode. Did you try to perform erase and read operations in Single SPI mode? Does the device give correct output? This will help us to confirm that hardware connections are fine.
  5. Can you please tell us the exact sequence of commands that you are following? Also tell the SPI mode in which you are sending each command.
  6. Have you implemented any kind of protection scheme on your flash device?
  7. Is the device responding correctly to any basic command such as read  device ID etc.? Could you try reading the device ID? It will help us confirm that the hardware connections are fine.

Regards.

 

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Hi,

Please find my response below in the same sequence to your queries.

  1. Yes Quad mode has been enabled on the device as device is giving correct response for the command (0xAF) for reading Quad ID. And reading back CR1 register also shows that Quad mode is set. And yes I am aware that after power cycle it will revert back to default.
  2. Yes I am sending address along with D8h command. I am using erase API provided by Nordic SDK so I will have to recheck this. Is this command supposed to run in Single SPI mode when I am trying to use read and write in Quad QSPI?
  3. I am trying this with single device only, we are trying to procure more chips as old ones got damaged while trying to writing configuration on non-volatile memory.
  4. We checked this before setting chip in QSPI mode and it was working fine. We will check the same with QSPI mode also.
  5. Please find the exact sequence of commands at the bottom of this message.
  6. No protection is used till now.
  7. We are able to read device ID and configuration registers. 

Sequence of commands followed.

  • read device ID
  • read SR, CR1, CR2, CR3
  • run WRENV
  • WRR
  • write SR
  • write CR1
  • write CR2
  • write CR3
  • write disable
  • read back CR1
  • read device ID again
  • read quad ID to verify on DSO.
  • send D8h command along with 0x00 in 3bytes in QSPI mode (1-4-4)(Used Nordic inbuilt erase function to perform this operation).
  • send EBh command along with 0x00 in 3bytes in QSPI mode (1-4-4) and read back the data(Used Nordic inbuilt read function to perform this operation)..
  •  
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AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi @abhishekps 

Yes I am sending address along with D8h command. I am using erase API provided by Nordic SDK so I will have to recheck this. Is this command supposed to run in Single SPI mode when I am trying to use read and write in Quad QSPI? Yes, the D8h command and the address for erasing should be sent in Single SPI mode. There is no Quad erase command. 

In the sequence of commands mentioned, I don't see any step for polling the WIP bit in Status Register. Are you aware of the polling requirement? Please see datasheet section "8.6.3 Block Erase (BE D8h or 4BE DCh)". The WIP bit implies the status of any embedded operations being performed on the flash. When a program/erase operation is initiated, the WIP bit gets set to 1 indicating that the program/erase operation is in progress. We need to keep polling (reading the SR) the WIP bit to check its value. When the WIP bit becomes 0, it indicates that the operation was successfully complete. Along with the WIP bit, it is also recommended to read the error bits (P_ERR and E_ERR). These bits get set in case an error happens while program/erase. In case of error, WIP bit also remains stuck at 1.

Please confirm whether you are polling the WIP and E_ERR bits after initiating erase operation or not? If not, kindly include the step in your code.

In case you are facing difficulty with third party SDK, I would also like to inform you about the Low Level Driver for Serial Flash from Infineon. You can download the sLLD from this link. A sample project that shows interfacing S25FL064L with PSoC 6 can be found on this link

Please let me know if you have any further questions. 

Regards.

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