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lestc_981471
Level 1
Level 1

Hi Guys,

I have downloaded the S25FL128S VHDL model (from http://www.cypress.com/simulation-models​), added to my project in Xilinx Vivado and tried to synthesize but got the following error message:"ERROR: [Synth 8-26] block statement with generics or ports not implemented".

It seems that Vivado can't synthesize the "Main Behavior Block" that has a port and port map inside.

I have searched everywhere but couldn't find much information about the Block statement and what I am doing wrong.

For VitalBuf and VitalWireDelay I got the following message: "WARNING: [Synth 8-312] ignoring unsynthesizable construct: non-synthesizable procedure call". In Vivado it also seems that these are not being found for some reason:

pastedImage_4.png

Could you please give some advice on that?

Thanks in advance,

Leonardo.

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SudheeshK
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hi Leonardo,

This model is designed to be used only for simulations. They are not synthesizable.

Thanks and Regards,

Sudheesh

View solution in original post

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SudheeshK
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hi Leonardo,

This model is designed to be used only for simulations. They are not synthesizable.

Thanks and Regards,

Sudheesh

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