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user_4199881
Level 1
Level 1

如图所示,用的是S25系列的16脚芯片,VCC和VIO分开供电的,因为信号端连接的FPGA的bank是1.9V供电,所以VCC是3.3V、VIO是1.9V,FPGA程序固化到flash上没问题,但是上电时候flash并没有把固化的程序烧录到FPGA上,FPGA型号是XC7K325T-2FFG900I。测量发现1脚、8脚(SO)、9脚(WP#)均为低电平。

我们软件工程师说不懂这一块,反正程序烧进去了就说明软件没问题,只能想万能的论坛求助了,望得到解答微信图片_20200515095520.png

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1 Solution

I found that it's a FPGA problem,I didn't use it right.pastedImage_0.png

R23 pin is a configration pin,which should be tied to Vcc14 through a resistor,while I left it fload.pastedImage_1.png

So the flash could do its job when I didn't use bank 14,when I use bank 14,it failed.

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4 Replies
AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi,

Thank you for contacting Cypress Semiconductor.

Could you please tell me whether the FPGA is using Single SPI or Quad SPI to read the flash? If Quad SPI is being used, can you please check whether Quad mode has been enabled on the flash?

Regards,

Apurva

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It's SPIX1 mode---single SPI mode.

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AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi,

Thank you so much for the clarification.

Could you please tell me the reason for keeping pin 1 (HOLD# signal) LOW? If you go to page 10 of the datasheet you will find the explanation of the HOLD# signal. Driving the HOLD# signal LOW pauses any serial communication with the device.

Regards,

Apurva

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I found that it's a FPGA problem,I didn't use it right.pastedImage_0.png

R23 pin is a configration pin,which should be tied to Vcc14 through a resistor,while I left it fload.pastedImage_1.png

So the flash could do its job when I didn't use bank 14,when I use bank 14,it failed.

0 Likes