S25FL128L Cyclone V Configuration

[XinYuSu]

Hello, I'm wondering if it's possible to use the S25FL128L-Series ICs as an active-serial configuration device for a Cyclone V FPGA. I found the AN200498 Application Note that gives instructions for usage with the S25FL128S series, which appears to be the 16-SOP equivalent of the 8-SOP S25FL128L.

The main difference appears to the the pinouts, and Reset# being tied with SIO3. If I were to disable the Reset # support via the non-volatile configuration register, would I be able to use it in the same way?

Thanks.

[BushraH_91 · Accepted solution]

Hello 

Thank you for contacting Infineon Technology. 

It is possible to use S25FL128L as an active serial configuration device for Cyclone V FPGA. S25FL128L also offers the same pinout SOIC16 package as S25FL128S. Please refer to Ordering Part Number in S25FL128L datasheet for the available packages. The command set is also compatible.

Regard to IO3/RESET# pin, RESET# function is default disabled. You don’t need to configure the non-volatile configuration register to disable it.

However, S25L128L and S25FL128S have different latency code definition and register bits definition. For example, S25FL128S has 2 bits default latency code 00b which support SDR read frequency up to 80Mhz. S25FL128L has 4 bits default latency code 1000b which support SDR read frequency up to 108MHz. So as in AN200498 chapter 3 instructed, Latency Code needs to be configured to support read at 100MHz. But it is not necessary for S25FL128L.

For Quad IO mode (i.e., AS4 mode), when assigning the 'QSPI Flash quad IO mode dummy clock' (step 6.h in AN200498 on page 5), it is 7 for S25FL128S (2 mode cycles + 5 dummy cycles when LC is configured as 10b). It should be 10 for S25FL128L (2 mode cycles + 8 dummy cycles when LC is default 1000b).

There might be some other slight differences for the configurations. Please refer to the attached AppNote and S25FL128L, S25FL128S datasheets for more detail.

Thank you

Regards,

Bushra