S25FL064L VHDL/Verilog model simulation in Modelsim doesn't give expected waveforms

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AI
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Hi, 

  • I have S25FL064L Chip connected to Altera MAX II FPGA.
  • My objective is to write a VHDL module to read/write words from/to the S25FL064L.
  • I tried simulating the provided model S25FL064L - VERILOG (cypress.com) with Cypress's testbench, however, I cannot make sense of the resulting waveform; SI is giving HIGH IMPEDANCE upon receiving READ CMD 0x03 from the stimulating testbench's signals.
    Is there anything I should configure before I read/write in this example testbench model?

AI_0-1630379022561.png

 

 

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8 Replies
Apurva_S
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100 likes received 500 replies posted 250 solutions authored

Hi @AI 

Could you please confirm whether you are using the SDF file while running the simulation or not?

Regards.

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AI
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No - when I generated these waveforms, it was just a behaviouralsimulation.

I tried adding the SDF file to the vsim command and I ran into another issue:

# usage: sdfcom [ options ] source-file output-file
# 
# Options:
# 
#   -32                 Run in 32-bit mode
# 
#   -64                 Run in 64-bit mode
# 
#   -mindelays          Use minimum timing from min:typ:max expressions
# 
#   -typdelays          Use typical timing from min:typ:max expressions (default)
# 
#   -maxdelays          Use maximum timing from min:typ:max expressions
# 
#   -delayscale <val>   Scale delays by the specified value
# 
#   -nocompress         Don't compress the resulting output file
# 
#   -suppress <msg(s)>  Suppress comma-separed list of error/warning messages
# 
# Loading work.s25fl064l(vhdl_behavioral_static_memory_allocation)
# ** Fatal: SDF files require Intel FPGA Edition primitive library
#    Time: 0 ps  Iteration: 0  Instance: /testbench_s25fl064l_vhdl File: C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/testbench_S25fl064l_vhdl.vhd Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./CPLD_U25_run_msim_rtl_vhdl_S25FL064L_TB.do PAUSED at line 26

 

Here is my .do simulation file:

#############
# VHDL ######
#############

transcript on
if {[file exists rtl_fmf]} {
	vdel -lib rtl_fmf -all
}
vlib rtl_fmf
vmap fmf rtl_fmf

vcom -93 -work fmf {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/conversions.vhd}
vcom -93 -work fmf {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/gen_utils.vhd}


if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vcom -93 -work work {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/spansion_tc_pkg.vhd}
vcom -93 -work work {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/S25fl064l.vhd}
vcom -93 -work work {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/testbench_S25fl064l_vhdl.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L maxii -L rtl_work -L work -L rtl_fmf -L fmf -voptargs="+acc" -sdftyp {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/s25fl064l_vhdl.sdf} testbench_S25fl064l_vhdl

#add wave *  
add wave -radix hex -position insertpoint sim:/testbench_S25fl064l_vhdl/*
add wave -radix hex -position insertpoint sim:/testbench_S25fl064l_vhdl/DUT/*
add wave -radix hex -position insertpoint sim:/testbench_S25fl064l_vhdl/DUT/Behavior/*

view structure
view signals
run 1.5 us
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AI
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Hello, any help here?
The CYPRESS Model Manual clearly says SDF files are not required for behavioral sim:

AI_0-1630724055863.png

 

and

AI_1-1630724077912.png

 

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Apurva_S
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100 likes received 500 replies posted 250 solutions authored

Hi @AI 

Apologies for the delay. I am discussing this internally.

Apurva_S
Moderator
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Moderator
100 likes received 500 replies posted 250 solutions authored

Hi @AI 

Apologies for the delay. I was discussing the question internally.

I would like to inform you that SDF file is required for simulation. The documentation needs to be updated accordingly, and we will be raising an internal request for the same. We regret the inconvenience it may have caused.

Did you try simulating using the SDF file? Did you face any issues?

Regards.

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AI
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Hi @Apurva_S ,

Thanks for looking into this and for your feedback. 

As I mentioned above in my first reply, when I used the SDF file, I ran into simulator issues.

 

Do you have any clue how to compile this SDF file in Modelsim Altera?

 

Thank you

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Apurva_S
Moderator
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100 likes received 500 replies posted 250 solutions authored

Hi @AI 

Could you please let us know what is the error message/issue that you ran into ? You should follow the process for including sdf file as per the specific simulation tool you are using.

Regards.

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AI
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Hi @Apurva_S , 
As I wrote in my reply on ‎Aug 31, 2021 10:11 AM, here is the error message:


# usage: sdfcom [ options ] source-file output-file
# 
# Options:
# 
#   -32                 Run in 32-bit mode
# 
#   -64                 Run in 64-bit mode
# 
#   -mindelays          Use minimum timing from min:typ:max expressions
# 
#   -typdelays          Use typical timing from min:typ:max expressions (default)
# 
#   -maxdelays          Use maximum timing from min:typ:max expressions
# 
#   -delayscale <val>   Scale delays by the specified value
# 
#   -nocompress         Don't compress the resulting output file
# 
#   -suppress <msg(s)>  Suppress comma-separed list of error/warning messages
# 
# Loading work.s25fl064l(vhdl_behavioral_static_memory_allocation)
# ** Fatal: SDF files require Intel FPGA Edition primitive library
#    Time: 0 ps  Iteration: 0  Instance: /testbench_s25fl064l_vhdl File: C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/testbench_S25fl064l_vhdl.vhd Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./CPLD_U25_run_msim_rtl_vhdl_S25FL064L_TB.do PAUSED at line 26


And these were the commands I ran in my simulation.do file:

#############
# VHDL ######
#############

transcript on
if {[file exists rtl_fmf]} {
	vdel -lib rtl_fmf -all
}
vlib rtl_fmf
vmap fmf rtl_fmf

vcom -93 -work fmf {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/conversions.vhd}
vcom -93 -work fmf {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/gen_utils.vhd}


if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vcom -93 -work work {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/spansion_tc_pkg.vhd}
vcom -93 -work work {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/S25fl064l.vhd}
vcom -93 -work work {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/testbench_S25fl064l_vhdl.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L maxii -L rtl_work -L work -L rtl_fmf -L fmf -voptargs="+acc" -sdftyp {C:/MyFiles/Google Drive/Jobs/Upwork/7-Azbil---USA/CPLD/E-Design/HDL/v01/rtl/testbench/S25fl064l/s25fl064l_vhdl.sdf} testbench_S25fl064l_vhdl

#add wave *  
add wave -radix hex -position insertpoint sim:/testbench_S25fl064l_vhdl/*
add wave -radix hex -position insertpoint sim:/testbench_S25fl064l_vhdl/DUT/*
add wave -radix hex -position insertpoint sim:/testbench_S25fl064l_vhdl/DUT/Behavior/*

view structure
view signals
run 1.5 us

 

Please let me know if this is the correct way to compile the sdf file (I'm not very sure I did it correctly above)

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