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can you help me with setting the latency cycles of memory read?
Frequency 100MHz
QSPI 4s-4s-4s SDR
I had set the CFGR2V to C2
Read command :- 0C to read memory data
- Read command : 0C --> ADDRESS : 0x00000020 ---> MODE: 0x0000000A --->read cycles 32 bit
Iam trying to read the memory data. I'm getting 85A5 A5A5A. Actual data is A5A5 A5A5 .
the image attached is of reading the quad spi data of data line 2 and 3 because 1s-1s-1s is working proper with frequency 100 Mhz in that we can observe its missing few cycles .
can you pls suggest what is the cause ?
Solved! Go to Solution.
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Hello Shraddha,
There is no Ordering Part Number (OPN) mentioned within your initial e-mail. Therefore, please refer to the SEMPER S25HL-T datasheet attached.
As you had already mentioned, you had set volatile Config Register-2 (CFR2V) is set to C2h. However, Config Register-2 (CFR2V) should be set to C8h:
Config. Register-2:
CFR2V[7]: 1 = 4 byte adrs.
CFR2V[6]: 1 = Data Width set to 4 wide (4x - Quad) - QPI Protocol
CFR2V[4:5]: 00 = remains as default values.
CFR2V[3:0]: 1000 = latency code, eight cycles (default)
(Continuous Read) mode cycles: 2
Please clarify your Config. Register-2 value, as C2h. I am not quite sure this is the correct value.
Best regards,
Albert
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Hello Shraddha,
There is no Ordering Part Number (OPN) mentioned within your initial e-mail. Therefore, please refer to the SEMPER S25HL-T datasheet attached.
As you had already mentioned, you had set volatile Config Register-2 (CFR2V) is set to C2h. However, Config Register-2 (CFR2V) should be set to C8h:
Config. Register-2:
CFR2V[7]: 1 = 4 byte adrs.
CFR2V[6]: 1 = Data Width set to 4 wide (4x - Quad) - QPI Protocol
CFR2V[4:5]: 00 = remains as default values.
CFR2V[3:0]: 1000 = latency code, eight cycles (default)
(Continuous Read) mode cycles: 2
Please clarify your Config. Register-2 value, as C2h. I am not quite sure this is the correct value.
Best regards,
Albert
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- In SDR Quad I/O transaction, the mode bit pattern is Axh and the next transaction is assumed to be
an additional SDR Quad I/O transaction that does not provide command bits.
can you help me up with this,what does this statement exactly means ?
actually i'm trying to Program memory within single transaction using command (PRPGE_C_1 02) for qspi but for some reason its writing perfectly only in one memory location and rest all memory location i'm getting data not expected as of now i was trying to write into two memory location 0x00000000 and 0x00000001 the above attached image is result memory window?
what is the issue?