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Shraddha
Level 3
Level 3
First solution authored 50 sign-ins 10 questions asked

1.I'am reading the device id in 1s-1s-1s mode
2.enable 3 byte to 4byte by B7 cmd
4. reading all the registers values (status register 1-00h, status register 2-00h,cfgr register 1-00h,cfgr register 2-88h,cgfr register 3-00h,cfgr register 4- 08h) by 65 cmd with respective addresses(32 bits-1f in hexadecimal ) with read cycle of 8 bits .
5.enable write to volatile registers (cmd 50)
6.write enable cmd 71 with address and data , first iam writing in cfgr 1 -data 02 bit[ 1] should be high to enable 1-4-4 mode
7.write to volatile register 50 cmd
8.write enable cmd 71 with address and data , then iam writing in cfgr 2 -data E8 bit[ 6] and bit [5] should be high to enable 4-4-4 mode, this I'am writing in 1-4-4 format then its is convert to 4-4-4
9. after writing into all the registers i'am reading cfgr 1 ans cfgr 2 the values it showing is for cfgr 1-22 and for cfgr 2-33 that all are wrong values can you tell what is the issue i checked value for status register's also after write immediately it showed the value 02 means write is happening but i'am not getting where the issue is , that registes read and write in diff diff mode i have done that properly and also checked thrice?
see the attached pdf  quer 2

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1 Solution
Shraddha
Level 3
Level 3
First solution authored 50 sign-ins 10 questions asked

can see the memory window and let me know what is the issue ?

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9 Replies
AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Shraddha,

Thank you for contacting Infineon Technologies.

Please verify and confirm the following:

1). After entering the 1-4-4 mode, verify and confirm Device ID is '342A1A0F.'  Use RDQID command : AFh

2). After programming Config. Register-2 (CFR2V) to E8h (4-4-4), verify and confirm that STR1V[5] and STR1V[6] are not set to 'ONE' (program/erase error flag).  Use RDSR1_0_0 Command : 05h

3). If STR1V[5],  STR1V[6] and STR1V[1] = ZERO (no error), verify and confirm value of Config. Register-2 (CFR2V) is actually E8h.  Use RDARG_C_0 command : 65h

Please let us know of your findings/results

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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Hello Shraddha,

You had indicated previously that the Latency Cycle is 00.  What is the frequency at which the S25HL512T is currently operating, now?

 

Best regards,

Albert

Infineon Technologies

 

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AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

      < CORRECTION >

Hello Shraddha,

   < CORRECTION MADE IN #2 - DISREGARD PREVIOUS MESSAGE >

Thank you for contacting Infineon Technologies.

Please verify and confirm the following:

1). After entering the 1-4-4 mode, verify and confirm Device ID is '342A1A0F.'  Use RDQID command : AFh

2). After programming Config. Register-2 (CFR2V) to E8h (4-4-4), verify and confirm that STR1V[5] and STR1V[6] are not set to 'ONE' (program/erase error flag).  Use RDSR2_0_0 Command : 0h

3). If STR1V[5],  STR1V[6] and STR1V[1] = ZERO (no error), verify and confirm value of Config. Register-2 (CFR2V) is actually E8h.  Use RDARG_C_0 command : 65h

Please let us know of your findings/results

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

< CORRECTION >

Hello Shraddha,

   < CORRECTION MADE IN #2 - DISREGARD PREVIOUS MESSAGE >

Thank you for contacting Infineon Technologies.

Please verify and confirm the following:

1). After entering the 1-4-4 mode, verify and confirm Device ID is '342A1A0F.'  Use RDQID command : AFh

2). After programming Config. Register-2 (CFR2V) to E8h (4-4-4), verify and confirm that STR1V[5] and STR1V[6] are not set to 'ONE' (program/erase error flag).  Use RDSR2_0_0 Command : 07h

3). If STR1V[5],  STR1V[6] and STR1V[1] = ZERO (no error), verify and confirm value of Config. Register-2 (CFR2V) is actually E8h.  Use RDARG_C_0 command : 65h

Please let us know of your findings/results

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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for cfgr 1 when iam writing 02 , its taking 22 TBPROT is also get set to bit 1 what does it mean?

 

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Write command itself not happening I checked by configuring other volatile registers say CFGR3 for read latency cycle its reading 00 . Do we need to look into the protection part?

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Shraddha
Level 3
Level 3
First solution authored 50 sign-ins 10 questions asked

WRENV(50 CMD) will only work with WRENB_0_0 cmd 01 not with WRENB_0_0 cmd 71 confirmation?

 

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AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Shraddha, 

The Write Enable Volatile command (WRENV_0_0 : 50h) works with Write Register command (WRR : 01h)

The Write Enable command (WRENB_0_0 : 06h) works with Write Any Register command (WRAR : 71h)

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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Shraddha
Level 3
Level 3
First solution authored 50 sign-ins 10 questions asked

can see the memory window and let me know what is the issue ?

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