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Hello -- I'm currently trying to program the NVM device but am getting bad data when read back.
For example:
- Executing a page programming command (PP) I am shifting in the PP command + 3 bytes of address (e.g. 24'h00_00_00)
- When I read the data back (READ command + 3 bytes of address) I get bad data on the device and also in the verilog simulation model I get X's. I have set the write enable latch before the program, and I can check that the 'Write in Progress' WIP bit is set as expected. I also wait until the WIP bit is deasserted to perform the read.
- When I perform an erase command (e.g. CE) and then I perform a READ + 3 bytes of address, I successfully read back all 1's in the real-time hardware and in the verilog simulation model. I also set the write enable latch prior to an erase.
Please help me understand if I am missing something to program the device. The device accepts other commands, including erase, but it programs bad data
Solved! Go to Solution.
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Hi,
I wanted to clarify more and want to correct my previous response
Can you please confirm if are following the following steps:
1) WREN (write enable )
2) Read Status register
3) If WIP ( Write in Progress ) bit is set (Please check this bit in status register read)
1 = Device Busy a Write Registers, program or erase operation is in progress
0 = Ready. Device is in standby mode and can accept commands.
4) Read Status register
5) Polling (You can follow following link for details on polling in flash : https://community.infineon.com/t5/Code-Examples/Status-Register-polling-for-Infineon-SPI-NOR-Flash/m... )
6) Read the data , if you are getting correct data.
Please let us know if are following the above steps.
Thanks and Regards,
Yuvraj
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Hi,
Thank you for contacting Infineon Technologies.
Can you do erase operation first and try to do page program.
Also can you please provide waveform of the operation you are performing.
Thanks and Regards,
Yuvraj
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Here a page program operation AFTER a chip erase in the verilog simulation model. I am shifting in the PP (02h) command + 3 bytes of a random address (04_76_0Ah) to program 4 bytes of data (7777h).
Here is the READ command (03h) + that same address (04_76_0Ah) after the write-in-progress bit has been deasserted. You can see the values are undefined in the verilog model.
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Hi,
After doing the Programming please read the status register (data polling) and check if you are getting any error bit.
If any error bit is set do again write enable and program , after that do data polling again.
You can use LLD provided by Infineon. I have attached LLD.
Regards,
Yuvraj
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Hi,
I wanted to clarify more and want to correct my previous response
Can you please confirm if are following the following steps:
1) WREN (write enable )
2) Read Status register
3) If WIP ( Write in Progress ) bit is set (Please check this bit in status register read)
1 = Device Busy a Write Registers, program or erase operation is in progress
0 = Ready. Device is in standby mode and can accept commands.
4) Read Status register
5) Polling (You can follow following link for details on polling in flash : https://community.infineon.com/t5/Code-Examples/Status-Register-polling-for-Infineon-SPI-NOR-Flash/m... )
6) Read the data , if you are getting correct data.
Please let us know if are following the above steps.
Thanks and Regards,
Yuvraj
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Issue has been resolved:
I don't remember exactly what it was, but if writing to the memory array gets locked out if the model is brought out of reset at the same time WP is assigned I think. The model will throw a setup timing violation and will lock programming.