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Nor Flash Forum Discussions

MuMc_2326662
Level 1
Level 1

We have a new board with a Xilinx Artix-7 FPGA and a Cypress S25FL128S SPI flash.  I exported a SVF file from Vivado (v2019.2) to be used with our Goepel JTAG tools for programming the S25FL128S device.  This seems to work fine, I can program the SPI flash and the Artix will configure from the SPI flash.  A requirement has come down where I need to lock the bottom 1/4 of the device.  According to the S25FL128S data sheet, I need to set the TBPROT OTP bit in the configuration register to 1 in order to lock the bottom 1/4.  As soon as I do this I can no longer program the SPI flash with the SVF file.  I read the status register and the BP[2..0] bits still read 000, so they are not locked.  The funny thing is, I can still program the SPI flash using Vivado directly.  I can also bit bang data into the flash using boundary scan.  I'm not sure why the SVF file works before setting TBPROT but does not after setting TBPROT.  I also created an SVF file that only contains the erase command.  It seems to work regardless if the TBPROT is set or not.  I am wondering if the program function in the SVF is reading the configuration register and expecting to be 0?  I have reached out to Xilinx, but they have been slow to respond. I was wondering if anyone has seen something like this?

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BushraH_91
Moderator
Moderator
Moderator
250 solutions authored First comment on blog 500 replies posted

Hello Murray,

Thank you for contacting Cypress Community Forum.

Please contact Xilinx since the issue is related to SVF file.

Thank you and have a nice day

Regards,

Bushra

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1 Reply
BushraH_91
Moderator
Moderator
Moderator
250 solutions authored First comment on blog 500 replies posted

Hello Murray,

Thank you for contacting Cypress Community Forum.

Please contact Xilinx since the issue is related to SVF file.

Thank you and have a nice day

Regards,

Bushra

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