For S25FL128S, how long is the byte program time?

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xiaowei_li_3787
Level 4
Level 4

Hi

I am using the flash chips of CYPRESS,S25FL128SAGNFI000, but I have some questions that i don't understand..

1, At the 9.10 of the datasheet, it says that the page program time (256 bytes) is 250us typ and 750 us max.

And Now I want to program just 32bits to the flash (with QPP command),  and how long is the program time?

Can I just think of the 32bits time as 250us*4/256=4 us?

2, At the QPP command of 9.5.3 of the datasheet , the datasheet says " It is recommended that a multiple of 16 byte length and aligned Program Blocks be written. This insures that Automatic ECC is not disabled."

Is it nessary that the data length must be a multiple of 16bytes? (like 16 bytes, 32bytes, 48......)

Now I just want to program 32bits(4bytes) with QPP command? Can my plan work?

3, Besides, about Question 1, I think the correct way of program is after my address and data sent into the flash, I should check the WIP bit to judge if the program operation is done. Is my understanding right?

But the questions now is that I want to know the program time of 32bits to judge if my design plan is feasible..

Looking forward to your reply and thank you very much.

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1 Solution

jahe​ 

Hi, Thank you so much for your help!

The program time about QPP 32bits is the most important thing that I want to know...  

1, It is shorter than 250us typ but not fast as 4 us. Since any programming operation requires internal preparation time for each programming operation, Cypress recommends to maximize using page programming buffer (256 bytes or 512 bytes).

--> Is there any way to estimate the 32bit QPP program time ? Or does the Cypress have some information about it ?

Or is there some max time about this?

(because I want to estimate the time needed that  all my data (4Mbytes) writen into flash with QPP command(32bit). And in my system, I can't program the whole page size bits, just 32 bits everytime.. ).

2,Your 32-bit (4-byte) should be programmed without any issue, but the automatic ECC for the data will be disabled.

--> I think,  without the automatic ECC, it wouldn't matter the QPP 32bit operation, it just doesn't have the data correct function. Is my understanding right?

Looking forward to your reply and Thanks again!

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8 Replies
Scott_Heo
Employee
Employee
25 sign-ins First question asked First like given

Hi Xiaowei,

I would like to copy your questions to write some comment about it.

1, At the 9.10 of the datasheet, it says that the page program time (256 bytes) is 250us typ and 750 us max.

And Now I want to program just 32bits to the flash (with QPP command),  and how long is the program time?

Can I just think of the 32bits time as 250us*4/256=4 us?

[Scott] It is shorter than 250us typ but not fast as 4 us. Since any programming operation requires internal preparation time for each programming operation, Cypress recommends to maximize using page programming buffer (256 bytes or 512 bytes).

2, At the QPP command of 9.5.3 of the datasheet , the datasheet says " It is recommended that a multiple of 16 byte length and aligned Program Blocks be written. This insures that Automatic ECC is not disabled."

Is it nessary that the data length must be a multiple of 16bytes? (like 16 bytes, 32bytes, 48......)

[Scott] If you need to use Automatic ECC enabled (it is for data in every 16-byte aligned with address 16-byte), a page program address has to be align with 16-byte and the length has to be a multiple of 16-byte as well.

Now I just want to program 32bits(4bytes) with QPP command? Can my plan work?

[Scott] Your 32-bit (4-byte) should be programmed without any issue, but the automatic ECC for the data will be disabled.

3, Besides, about Question 1, I think the correct way of program is after my address and data sent into the flash, I should check the WIP bit to judge if the program operation is done. Is my understanding right?

[Scott] Yes correct. You need to poll Status Register's WIP bit (using a kinf of status polling loop) to judge if a programming operation has been completed.

But the questions now is that I want to know the program time of 32bits to judge if my design plan is feasible..

[Scott] I don't recommend you to judge a programming completion by using a programming time estimated. The next SPI operation (except status register read command or reset command) will be ignored unless the existing programming operation is completed.

Best regadrs,

Scott

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jahe​ 

Hi, Thank you so much for your help!

The program time about QPP 32bits is the most important thing that I want to know...  

1, It is shorter than 250us typ but not fast as 4 us. Since any programming operation requires internal preparation time for each programming operation, Cypress recommends to maximize using page programming buffer (256 bytes or 512 bytes).

--> Is there any way to estimate the 32bit QPP program time ? Or does the Cypress have some information about it ?

Or is there some max time about this?

(because I want to estimate the time needed that  all my data (4Mbytes) writen into flash with QPP command(32bit). And in my system, I can't program the whole page size bits, just 32 bits everytime.. ).

2,Your 32-bit (4-byte) should be programmed without any issue, but the automatic ECC for the data will be disabled.

--> I think,  without the automatic ECC, it wouldn't matter the QPP 32bit operation, it just doesn't have the data correct function. Is my understanding right?

Looking forward to your reply and Thanks again!

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Hi Xiaowei,

1, It is shorter than 250us typ but not fast as 4 us. Since any programming operation requires internal preparation time for each programming operation, Cypress recommends to maximize using page programming buffer (256 bytes or 512 bytes).

--> Is there any way to estimate the 32bit QPP program time ? Or does the Cypress have some information about it ?

Or is there some max time about this?

(because I want to estimate the time needed that  all my data (4Mbytes) writen into flash with QPP command(32bit). And in my system, I can't program the whole page size bits, just 32 bits everytime.. ).

[Scott] I agree that the typ and max time for programming 4-byte can be estimated under some conditions. But I believe this cannot be used in all cases nor become generalized due to aging of devices, operation temperature and so on. If there is no option you have, I think the max value of 256-byte page programming (750us) would be safe, but quite slow for your system...

2,Your 32-bit (4-byte) should be programmed without any issue, but the automatic ECC for the data will be disabled.

--> I think,  without the automatic ECC, it wouldn't matter the QPP 32bit operation, it just doesn't have the data correct function. Is my understanding right?

[Scott] Your understanding is right. You can use any address and any length (less or equal to 256-byte) for page programming without the automatic ECC. The automatic ECC of Cypress SPI flash memory is an 'additional' feature for data integrity, not a mandatory for a user to keep data 20 years without any bit error.

Best regards,

Scott

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jahe

Hi, Thank you for your reply.

1,I agree that the typ and max time for programming 4-byte can be estimated under some conditions. But I believe this cannot be used in all cases nor become generalized due to aging of devices, operation temperature and so on. If there is no option you have, I think the max value of 256-byte page programming (750us) would be safe, but quite slow for your system...

--->Emmm, if I take the 750 us for the 32bit program time, it would be too slow for my system to use....

I found the datasheet of S25FL128L at the Cypress , (my chip this time is S25FL128SAGNFI000) , there are some illustrations about the program time, such as tBP1, tBP2, and according to the Notes of the figure, I can calculate the program time of several bytes.

(But these parameters are not included in the datasheet of S25FL128S )

Because it is different from my chip tpye, but I think they are similar. Can I take the time below to estimate my program time?

12123.PNG

2, Besides, I am really sorry to bother you , I want to ask something else .

At the datasheet about QOR 9.4.4, the datasheet says "Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal."

I have some doubt about the SCK.

Is it recommonded that the SCK must be a constant frequency?

Or I can change the frequency of SCK , such as the interval of the two SCK falling edge is different from the next two SCK falling edge(in one QOR command ) ?

Thank you so much for your help and looking forward to your reply~

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Scott_Heo
Employee
Employee
25 sign-ins First question asked First like given

Hi Xiaowei,

Thanks for asking great questions I hope my answer would be helpful for your engineering!

I found the datasheet of S25FL128L at the Cypress , (my chip this time is S25FL128SAGNFI000) , there are some illustrations about the program time, such as tBP1, tBP2, and according to the Notes of the figure, I can calculate the program time of several bytes.

(But these parameters are not included in the datasheet of S25FL128S )

Because it is different from my chip tpye, but I think they are similar. Can I take the time below to estimate my program time?

[Scott] The flash memory technology of S25FL128S (FL-S) is based on SONOS (silicon-oxide-nitride-oxide-silicon) technology + MirrorBit technology to store two bits in one memory cell, while S25FL128L (FL-L) is designed based on Floating-Gate structure. Those names are similar but actually those fundamental technologies are quite different. I don't recommend you to take the time from FL-L WRR command's time. I'm sorry about it.

At the datasheet about QOR 9.4.4, the datasheet says "Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal."

I have some doubt about the SCK.

Is it recommonded that the SCK must be a constant frequency?

Or I can change the frequency of SCK , such as the interval of the two SCK falling edge is different from the next two SCK falling edge(in one QOR command ) ?

[Scott] Right, the SCK must be a constant frequency per each SPI operations (you also need to consider the Latency Code if you want to use different frequency at run-time). Based on the table 12 (for SDR) and table 13 (DDR), you will find that those clock high/low time should be within 45% of SCK clock period. That implies changing the frequency may be allowed within plus/minus 10% of SCK frequency. But practically, changing the frequency of SCK slower works (do not make it faster - which makes the SCK frequency looks higher than its specification). In this case, you may need to consider when the flash memory controller samples the each output (data read) respectively.

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Best regards,

Scott Heo

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jahe​ 

Hi, Thank you for your reply!

About Question1, So there is no other way to judge the 32bit QPP program time?   T^T

About Question 2, I mean the SCK is like this, Can this SCK be available for the flash chip?

(the frequency of SCK is not constant.)

12125.PNG

Thank you so much for your help and looking forward to your reply~

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Scott_Heo
Employee
Employee
25 sign-ins First question asked First like given

Hi Xiaowei,

There is no way to judge an optimal QPP completion time without a Status Register polling.

It is not supported officially since it is out of specification. Hence Cypress won't guarantee any abnormal operation caused by this. But practically it may work - the SPI clock frequency above (50 MHz) is slower than QPP clock limitation on a specification. But again, it is highly recommended to keep the constant clock frequency for guaranteed operation  Thank you!

Best regards,

Scott

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jahe

Hi , Thank you so much for your help!

I understand what you said.

It really helps a lot!  Thanks again!

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