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xiaowei_li_3787
Level 4
Level 4

Hi

I am using the flash chip of CYPRESS,S25FL128SAGNFI000, but I have some questions that i don't understand when I do the simulation.

I am doing the simulation of QPP command, but when I do the QPP command for several times , there are some of the cases that indicate there is a program error happen.

but these cases are the same except the address and the write data, So could you help me to find out why the program errors happen?

(the commadn execution is this:

the system send the qpp signal, then the FLASH control module send the commands to the flash chip like this sequence:

1, WREN+RDSR1 (make sure that the WEL is enable)

2, QPP+ADDRESS+DATA(quad mode, 32bit data )

3, RDSR1(polling to check the WIP )  )

But,

1, I do the qpp command like 6 times , the only differece between these cases is the different address and  different wite data.

But just like the figure, at the 2nd and 3rd time, the program error happened.

cyc2.PNG

and  after the QPP + ADDRESS+DATA, then the first RDSR1, the SR1[6] is 1...

cyc.PNG

But I don't know why the program error happened...

Could you help me with the question?

Thanks again and looking forward to your reply~~~

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1 Solution

Hi Xiaowei,

QPP and PP can both use for data programming, the difference is only transferred through single or quad lines. For your application to program 32bit every time, there is not much performance improvement by using QPP than PP, QPP will have better performance for large size data programming.

Thanks,

Ryan

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7 Replies
RyanZhao
Moderator
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750 replies posted 100 sign-ins 100 likes received

Hi Xiaowei,

For this case, the program error happened (SR1[6] P_ERR=1) during the QPP command, so it may possible from the following reasons:

• Programmed protected area:

Although they provided some bit fields value of SR1, there is no BP(Block Protection) related fields values in the snapshot, better provide entire value of SR1 when issue happening.

pastedImage_0.png

• QUAD mode configuration:

Please check about the QUAD mode configuration in CR1

• Clock speed and SPI mode:

The SCK clock speed for QPP is different with clock of RDSR1 and WREN, why? The max speed of QPP is 80MHz. What’s the SPI mode they are using now? Our flash only support Mode 0 and 3.

pastedImage_2.png

Thanks,

Ryan

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rzzh​ 

Hi, Thank you so much for your reply! (Sorry for my late reply because I just came back from a business travel)

The answers are as follows:

1,Programmed protected area:Although they provided some bit fields value of SR1, there is no BP(Block Protection) related fields values in the snapshot, better provide entire value of SR1 when issue happening.

------> I didn't set the BP0-BP2 bit, because I just don't need the BP function this time, so when the issue happened or not , the SR1 BP0-BP2 bits are 0

01021.PNG

2, QUAD mode configuration:Please check about the QUAD mode configuration in CR1

------>Before the WRR QPP command, I do the WRR command and write the SR1[00H] and CR1[86H] to set the CR1(Latency Code=10 and QUAD = 1), so I think the QUAD mode is correct.

01022.PNG

3,Clock speed and SPI mode:The SCK clock speed for QPP is different with clock of RDSR1 and WREN, why? The max speed of QPP is 80MHz. What’s the SPI mode they are using now? Our flash only support Mode 0 and 3.

------> About the different SCK speeds, I thought the RDSR1 and WREN can be executed at the 100MHz, so the command of RDSR1 run at 100MHz and the QPP run at 50MHz ( to decline the whole operation time).

About the SPI mode , when the chip is in standby mode and not doing any operation, the SCK will stay at logic high(I think it is Mode 3)

Besides the discussion, the most strange thing is there are six times of the same QPP operations, but only at the 2nd and 3rd time the error happened.

the six times of address and write data are as followes:

1,  FL_ADDRESS_tmp <= X"000000";

    FL_WDAT_tmp  <= X"12341122";

2,  FL_ADDRESS_tmp <= X"000004";

    FL_WDAT_tmp  <= X"23451122";

3,  FL_ADDRESS_tmp <= X"00000C";

    FL_WDAT_tmp  <= X"34561122";

4,  FL_ADDRESS_tmp <= X"0048D0";

    FL_WDAT_tmp  <= X"45671122";

5,  FL_ADDRESS_tmp <= X"0159E0";

    FL_WDAT_tmp  <= X"56781122";

6,  FL_ADDRESS_tmp <= X"01E268";

    FL_WDAT_tmp  <= X"67891122";

I can't figure out why this phenomenon happened...

Could you help me with that?

Thank you so much and looking forward to your reply~~

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rzzh

Hi, I did some more test just now, and I found that the errors may be related with the program address.

(some premises:

1, every time I do the QPP command, there are 4 bytes(32bits) data writen into the chip

2, Though I write 32bits every time, but I still want to write these all data into the flash in sequence ( there are no spaces between the flash data )

)

For example, when the first QPP address is "000000" and the first QPP command is executed correctly, if the second QPP address is "000100", then the QPP command will fail, but if the second QPP address is "000104", the QPP command will be done correctly.

But I check it in the datasheet and the datasheet 9.5.3 quad page program, it says"It is possible to program from one bit up to a page size in

each Page programming operation.", so I don't think my operations are wrong...

From this phenomenon, could you help to give me some advice?

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rzzh​ 

Hi , I am so sorry to bother you, but if you have any messages about my question, please let me konw as soon as possible.

Thanks again..

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Are you using Cypress Verilog model? If so, which version?

Cypress latest version is at:

http://www.cypress.com/verilog/s25fl128s-verilog?source=search&cat=software_tools

In this version V1.24, there is some reversion history mention about the QPP command:

v124.jpg

The reason that the QPP should not program less than 1 page (16-byte) is because we have the ECC unit for every 16bytes, each unit have the ECC syndrome and ECC enable bit, program multiple time (even with different address) within the same page without erase operation will disable the internal ECC.

For more information about the internal ECC in FL-S series, please refer the following AN:

http://www.cypress.com/documentation/application-notes/an200731-automatic-ecc-cypress-65-nm-fl-s-mir...

Roy Liu
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Hi,

Thank you so much for your reply!

I checked the version of my simulation model(I am using the s25fl128s.vhd), I found that I downloaded the model at 2018/10/12, the version is

V1.15.

01251.PNG

01252.PNG

And I downloaded the latest simulation model from your link, it is V1.16, which added the QPP command part.

(I just didn't expect that the versions have been updated so fast 🙂

And  I think I know why this error happened.

01253.PNG

Besides, there is one more question that I want to confirm.

If I want to do the operation of programming 32 bits data everytime at the continuous address, I think I should use the PP command instead of the QPP command, is my understanding correct?

Thank you very much for your help! That really helps a lot!

And I am looking forward to your reply about my last question.

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Hi Xiaowei,

QPP and PP can both use for data programming, the difference is only transferred through single or quad lines. For your application to program 32bit every time, there is not much performance improvement by using QPP than PP, QPP will have better performance for large size data programming.

Thanks,

Ryan

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