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Hello.
The customer found discrepancies between the behavior of the simulation model and the description in the datasheet.
Device is S28HS512TGABHI010.
And they use “Infineon-VERILOG_S28HS512T-SimulationModels-v08_00-EN.zip” as simulation model.
Please confirm attached pptx file for their differences and customer’s questions.
Best Regards.
YuMa
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Hi,
In DDR mode, DS should be edge aligned with the data (Can refer to section 4.8.4 in the datasheet).
Any alignment with the clock can be ignored. It might due to the clock speed, delays or simulation settings.
Hope it clarifies your doubt.
Regards,
Yuvraj
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Hi,
Thank you for contacting Infineon Technologies.
Thank you for pointing out bug in the Verilog model.
The DS signal should start toggling in sync with the rising edge of the CK signal as per datasheet which is correct.
Thanks and Regards,
Yuvraj
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Yuvraj-san.
Thank you for your response.
Are both Q1(edge to synchronize) and Q2(AC specs of tdss/tdsh) bugs of simulation model?
If they are bugs, please release a fixed simulation model.
Best Regards.
YuMa
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Yuvraj-san.
Could you please answer below questions.
Q1)
Are both Q1(edge to synchronize) and Q2(AC specs of tdss/tdsh) of customer’s pptx file bugs of simulation model?
Q2)
If they are bugs, please release a fixed simulation model.
Could you please let us know when these bugs will be fixed?
Best Regards.
YuMa
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Hi,
A data strobe (DS) is transmitted externally, along with data, for use in data capture at the host. During the period of data transfer in read transactions, the DS signal is driven by the device and transitions with the DQ signal data transitions. DS is used as an additional output signal with the same timing characteristics as other data outputs but with the guarantee of transitioning with every data bit transferred. DS is edge-aligned with data for DDR READs and is center-aligned with data for SDR READs. A pre-drive on DS exists to ensure DS is driven LOW
immediately after 2.5 clock cycle after last address byte input to the device.
DS should be edge aligned with the data in DDR mode.
We are looking at the issue of Tdss and Tdsh.
We will get back to you by end of this week.
Regards,
Yuvraj
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Yuvraj-san.
Thank you for your support.
The only thing you couldn't reproduce was Q2(AC specs of tdss/tdsh), Q1(edge to synchronize) was able to reproduce and confirmed the simulation model issue.
Is above my idea correct?
Let me check, just in case.
Best Regards.
YuMa
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Hi,
Q1 is already been answered in my previous reply
A data strobe (DS) is transmitted externally, along with data, for use in data capture at the host. During the period of data transfer in read transactions, the DS signal is driven by the device and transitions with the DQ signal data transitions. DS is used as an additional output signal with the same timing characteristics as other data outputs but with the guarantee of transitioning with every data bit transferred. DS is edge-aligned with data for DDR READs and is center-aligned with data for SDR READs. A pre-drive on DS exists to ensure DS is driven LOW
immediately after 2.5 clock cycle after last address byte input to the device.
DS should be edge aligned with the data in DDR mode.
Clock and DS are not directly related.
Thanks and Regards,
Yuvraj
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Yuvraj-san.
Sorry, I thought there is simulation model bug because I got the following answer first from you, but does it mean that simulation model behavior is actually correct?
>> The DS signal should start toggling in sync with the rising edge of the CK signal as per datasheet which is correct.
In datasheet, the transition of DQ and DS starts from the rising edge of CK.
However, in simulation waveform, the transition of DQ and DS starts from the falling edge of CK.
Is it correct to understand that both datasheet and simulation are correct since signals of DQ and DS are synchronized at the edge of CK? (It doesn't matter if it rising or falling)
Is it correct to understand that whether the timing at which DQ and DS start transitioning is the rising edge or falling edge of CK depends on the communication timing of the host?
Is it correct to understand that the edge of CK when DQ and DS start the transition is not fixed?(CK start edge will be rising or falling)
----------------------------------------
Datasheet description => DDR protocol, command, address and data inputs are latched on both edges of the clock, and data is output on both edges of the clock.
----------------------------------------
Best Regards.
YuMa
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Hi,
For Q2 we would like to know the configuration settings and command you are using.
DS is edge aligned to the data. tDSS and tDSH are both 1ps.
Thanks and Regards,
Yuvraj
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Yuvraj-san.
About Q2.
I am currently checking with the customer.
About Q1.
The original question was about the rising edge and falling edge of CK.
(Why is there a difference on the first edge of the clock?)
Please answer below question.
=======================================================
In datasheet, DQ transition starts from the rising edge of CK.
However, in simulation waveform, DQ transition starts from the falling edge of CK.
Is it correct to understand that whether the timing at which DQ start transitioning is the rising edge or falling edge of CK depends on the communication timing of the host?
Is it correct to understand that the edge of CK when DQ start the transition is not fixed because mode is DDR?(CK start edge will become rising or falling)
=======================================================
Best Regards.
YuMa
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Hi,
You needs to use the data strobe to capture the read data. The relation between DS and the clock is as per the Figure 81 in the datasheet.
tCKDS Max = 5.45 ns, tv Max = 5.45 ns
DQ and DS are edge aligned. tDSH = +/- 0.4ns and tDSS =+/- 0.4 ns
Regards,
Yuvraj
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Yuvraj-san.
Thank you for your response.
But first of all, I would like you to answer the original question regarding clock edges.
Please confirm P1 of “Questions_SemperOctal_SimModel.pptx” again.
In the datasheet, the first clock edge is rising edge.
However, in the simulation model, the first clock edge is falling edge.
Why is there a difference on the first edge of the clock?
Could this be a bug in the simulation model?
Or does it mean that there is no particular rule for the first clock edge in DDR mode, and it doesn't matter if the first clock edge is rising edge or falling edge?
(In other words, although there is first clock edge difference between the datasheet and the simulation model, both are correct.)
Best Regards.
YuMa
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Hi,
In DDR mode, DS should be edge aligned with the data (Can refer to section 4.8.4 in the datasheet).
Any alignment with the clock can be ignored. It might due to the clock speed, delays or simulation settings.
Hope it clarifies your doubt.
Regards,
Yuvraj