Nor Flash

[Ken]

Hi everyone,

we use the S25HL512T  with QUAD-SPI interface and find some issue about QPI read.

some test pattern as follow:

[Test pattern]

Write 256 bytes Data

Data  pattern1  : { 0x00, 0x01, 0x02 ... 0xFD, 0xFE, 0xFF }

Data  pattern2  : { 0xFF, 0xFE, 0xFD ... 0x02, 0x01, 0x00 }

[Write Command]

0x02

[Read Command]

0xEB (SDR) or 0xED (DDR)

[Erase Command]

0x20

[Protocol]

QPI SDR or DDR

[Address Byte Length]

3 bytes or 4 bytes

When we read the 256-byte data, once read a byte is 0x0F or 0xF0, behind 0x0F or 0xF0 data became abnormal.

Does somebody encounter the same problem?

[AS_36]

Hi @Ken 

Are you performing the program operation across page boundaries? I would like to inform you that the default size of the program buffer is set to 256, means page boundaries occur at every 256th memory location. If the page boundary is crossed during the page program operation, the address gets wrapped and programming starts from the starting of that particular page. Can you confirm that your program operation is not crossing page boundaries?

Regards.

[Ken]

Hi,

We tested these addresses

QSPI_32Send4_CMD(S25HS_PageProgram, 0x00010000, 0, QSPI_ADDRESS_4_LINES, QSPI_DATA_4_LINES, 256);

QSPI_32Send4_CMD(S25HS_PageProgram, 0x00004000, 0, QSPI_ADDRESS_4_LINES, QSPI_DATA_4_LINES, 256);

QSPI_32Send4_CMD(S25HS_PageProgram, 0x00001000, 0, QSPI_ADDRESS_4_LINES, QSPI_DATA_4_LINES, 256);

Nothing different.

These addresses shall not have any across page problem.

Use 256 Byte Write Buffer Size. (default: 0)

[AS_36]

Hi @Ken 

I would like to point out that there is difference between Quad SPI mode and QPI mode.

Quad mode is enabled by the below configuration register bit

QPI mode is enabled by the below configuration register bit

Could you please confirm which mode are you using?

Regards.

[Ken]

Hi,

We already set these register bits, the QPI and 4 bytes address,  it works.

And we tried to adjust the clock rates at 20 MHz, 1 MHz and 500 KHz.

It is still the same.

[Ken]

Hi,

We set the output drive impedance register to 001 (120 ohms), which is normal.

Who can help explain the details about the settings?

Why does it cause it to read the failed value (read a byte is 0x0F or 0xF0)?

[AS_36]

Hi @Ken 

IOIMPD[2:0] bits are required to select the IO driver output impedance. It is used to adjust the drive strength to meet the systems signal integrity requirements.

1. Can you please tell how are you confirming that the program operation was successful? Are you capturing the SPI signals?
2. If yes, can you provide the screenshots of the waveform for page program as well as read operations? 
3. Also provide the exact sequence of commands that you are following.
4. How many devices are showing this behavior? 
5. Is it possible that you may have performed excessive number of program/erase operations on the particular memory location being used for testing, such that you may have exhausted all the P/E cycles for that particular location?

Regards.

[Kent_Lee]

3. I can provide the sequence, if we don't configure the 120 ohm impedance.

The reading process became abnormal, even read ID command, because it has an 0x0F value.

the sequence

printf("Impedance\r\n");
S25HS_Write_Enable();
Data = S25HS_Read_Reg(REG_ADDR_CONG4);
Data |= (1 << 5);  //used 120 ohm
S25HS_Write_Reg(REG_ADDR_CONG4, Data);
S25HS_Read_Reg(REG_ADDR_CONG4);

printf("QPI\r\n");
//Set QPI mode and 4 bytes addressing for 512M bit = 64 MB
Data = S25HS_Read_Reg(REG_ADDR_CONG2);
S25HS_Write_Enable();
Data = (Data | 0xC0); // 4 bytes
//Data = (Data | 0x40); // 3 bytes
S25HS_Write_Reg(REG_ADDR_CONG2, Data);
S25HS_Busy4_Wait();

S25HS_32Read4_Reg(REG_ADDR_STAT1);
S25HS_Write4_Enable();
S25HS_32Read4_Reg(REG_ADDR_STAT1);
printf(" Erase \r\n");
//S25HS_Erase_Sector(0x03F00000);

S25HS_Erase_Block(0x03FF0000);
//S25HS_Erase_Chip();
S25HS_Busy4_Wait();
printf("D %08X D\r\n", S25HS_QuadSPI_Read_Test256());

printf(" Read \r\n");
TIM10->CNT = 0;
S25HS_QuadSPI_Read_Test256();
TS = TIM10->CNT;
printf("~~~~ TS :%d us\r\n", TS);

[AS_36]

Hi @Kent_Lee 

Apologies for the delay in responding.

We would need some more information.

1. How many chips showed this issue? Did you try to perform A-B-A test to see whether the issue follow with chip or board?
2. Can you try to use FAST READ other than QPI mode I/O read to see whether it’s the same behavior or not?
3. Did you try to perform READ_ID command in SPI mode or QPI mode? If the issue happened in QPI mode, can you try to restore to SPI mode and try again? Normally the RDID command should work in all cases without configurations.

Regards.