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Nor Flash

Infineon_User
New Contributor II

Hello Everyone:

      We are not able to set 'WEL' bit in Status Register 1, or even read back what is written in Memory. We are using a FPGA to interface with Serial Flash S25FL256S... . Below is the sequence of operations.

 

  • Power up
  • Wait for Tpu of 300us
  • Read JEDC ID (Instruction 0x1F). Correct data is read back.
  • Issue WREN (Instruction 0x6)
  • Issue Erase Flash Array (Instruction 0x20, address bits[23:0] = 0x0)
  • Wait for 11 seconds
  • Issue Status register read (RDSR Instruction 0x05), reads back 0x0. Expect WEL (bit 1 to be set since WREN was issued).
  • Issue Page Program (PP, Instruction 0x2, address[23:0] = 0x0, 4 Bytes of data).
  • Wait for 2 ms (for page program to complete).
  • Read Status 1 register, reads back 0x0.
  • Read Flash Array (Instruction, 0xB, address [23:0] = 0x0, ), reads back 0xFF all bytes. So data could not be stored.

    I am attaching some waveforms showing the operations.  The file names of waveforms indicate the type of operation being performed. These waveforms are from Xilinx Vivado ILA. The signal names are mapped as below.

SCK:                      jb_cp_mem_clk_OBUF

CS#:                      cp_pMem_csN_OBUF

IO[3:0]:                cp_mem_in_OBUF[3:0]

 

Below is some information about the operations shown in the waveforms.

1) Read JED ID & Issue WREN.jpg:    This file shows that reading of JEDEC ID is working. After reading the ID, we are issuing 'WREN' Instruction to set the 'WEL' bit.

2) Erase Flash Array (P4E).jpg:     Before writing we are erasing the sector at address 0x0.

3) Read Status register 1, RDSR1 .jpg:    Reading Status Register 1, read back data is 0x0.

4) Page Program & Read Status Register.jpg:   Write data to memory and read Status Register 1, read back data is still 0x0, WIP bit not set.

5) Read Status Register & Read Flash Array.jpg:  Read status register and read data from memory. Status register is still 0x0 and data read from memory is all 0xFF. Four bytes were written and four bytes read back.

     Did we miss anything from the datasheet? Are we doing something incorrectly? Please help!

Thank you so much.

Best regards,

 

 

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1 Solution
Infineon_User
New Contributor II

Hello:

      I was able to get SPI write and read to work by increasing delay between the time when CS# is asserted. I am testing Dual I/O and Quad I/O modes next.

     Thank you so much.

Best regards,

View solution in original post

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3 Replies
Infineon_User
New Contributor II

Hello:

      I was able to get SPI write and read to work by increasing delay between the time when CS# is asserted. I am testing Dual I/O and Quad I/O modes next.

     Thank you so much.

Best regards,

View solution in original post

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Ronak
Moderator
Moderator

Hello,

Can you please confirm that you are able to perform the operation after increasing the delay when the CS# is asserted?

Thanks,
Ronak

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Infineon_User
New Contributor II

Hello:

     Yes, SPI mode operations are working. I am also able to read in Dual SPI and Quad SPI mode. I am testing writes in Dual SPI and Quad SPI modes next.

     Thank you so much.

Best regards,

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