Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
camino
Level 4
Level 4
Distributor - TED (Japan)
5 solutions authored 10 replies posted First solution authored

Do we need to set FREEZE bit  to "1"  by WRR command in parallel in case we want to write other bits (includes in OTP bits) in CR1 correctly ?     After the writing,  are data of OTP bits in CR1 fixed (no change)  permanently ?   

In case of FREEZE bit  "0" , are there any possibility OTP bits in CR1 may be variable ? 

Best regards,

 

 

0 Likes
1 Solution
YukaA_81
Employee
Employee
5 solutions authored 10 replies posted First like given

Hi TED080713, Albert

I have additional comment.

The function of the FREEZE bit is "Lock current state of BP2-0 bits in Status Register, TBPROT and TBPARM in Configuration Register, and OTP regions".
BP2-0, TBPROT, and TBPAR are OTP bits, so once they are changed from 0 to 1, they cannot be changed back to 0.
Therefore, to prevent unintentional changes(0->1), they can be optionally locked with the FREEZE bit=1. However, since the FREEZE bit is volatile, it is only effective during power ON. Also, setting FREEZE bit is NOT mandatory.

Please note that even if only CR1 is changed in WRR execution, it is necessary to specify the data together with SR1 as shown in the flow below.

YukaA_81_0-1697505893766.png

regards,

IFX) Yuka Ami

View solution in original post

0 Likes
4 Replies
AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello,

Thank you for contacting Infineon Technologies.

When setting the FREEZE bit to "1" the OTP bits are set permanently, and can no longer be changed.  Once the OTP  bit has been programmed to "1", any attempt to erase back to "0" will result in a program error.

As long as the FREEZE bit remains at the default setting of "0", the other bits of the Configuration Register-1 (CR1) including FREEZE, are writable, and the OTP address space is programmable.

 

Best regards,

Albert

Infineon Technologies

 

 

 

0 Likes
YukaA_81
Employee
Employee
5 solutions authored 10 replies posted First like given

Hi TED080713, Albert

I have additional comment.

The function of the FREEZE bit is "Lock current state of BP2-0 bits in Status Register, TBPROT and TBPARM in Configuration Register, and OTP regions".
BP2-0, TBPROT, and TBPAR are OTP bits, so once they are changed from 0 to 1, they cannot be changed back to 0.
Therefore, to prevent unintentional changes(0->1), they can be optionally locked with the FREEZE bit=1. However, since the FREEZE bit is volatile, it is only effective during power ON. Also, setting FREEZE bit is NOT mandatory.

Please note that even if only CR1 is changed in WRR execution, it is necessary to specify the data together with SR1 as shown in the flow below.

YukaA_81_0-1697505893766.png

regards,

IFX) Yuka Ami

0 Likes
camino
Level 4
Level 4
Distributor - TED (Japan)
5 solutions authored 10 replies posted First solution authored
Hi Yuka-san, Albert-san,

Thanks for your appreciate comment.
Our customer left FREEZE bit default (0) at CR1 writing so OTP bits was unstable. We will ask them to set FREEZE bit to 1 in case write CR1.

Best regards,
H. Kamijima/TED
0 Likes
YukaA_81
Employee
Employee
5 solutions authored 10 replies posted First like given

Hi Kamijima-san,

Since the details of the phenomenon at the customer and its background are unknown, we cannot say that setting the FREEZE bit to 1 will solve this problem.
To get qualified advice, we recommend that you make a request at Technical Case system or consult a local FAEs.

regards,
Yuka Ami

0 Likes