Address latch timing for S29GL

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HiKu_1337496
Level 5
Level 5
Distributor - TED (Japan)
10 solutions authored 100 sign-ins 50 questions asked

Hi,

Please allow me to confirm the address latch timing for the S29GL.

[A] S29GL064N90TFI020
[B] S29GL064S70TFI020

 

[Q1]
Section 8.2 of [A]'s datasheet states "All addresses are latched on the falling edge of CE#".
Is there any timing for address latch other than CE# falling?
I would like to confirm the address latch timing when CE# falls before the address is determined.

[Q2]
The [B]'s datasheet no longer mentions "All addresses are latched on the falling edge of CE#".
Is the timing at which the address is latched different for [B] than for [A]?
Please tell us when the address is latched.

 

Best Regards,
Kumada

 

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1 Solution
Yuvraj
Moderator
Moderator
Moderator
250 replies posted 25 likes received 100 solutions authored

Hi,


Thank you for contacting Infineon Technologies.

Q1-->Ans.)  address should be placed on the bus at least before (or equal) CE# low since the address is latched at CE# falling edge. 

Q2-->Ans.) It doesn't describing a specific timing, but those GL-N and GL-S need address latching at CE# falling edge.

Hope it helps.

 

Regards,

Yuvraj 

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6 Replies
Yuvraj
Moderator
Moderator
Moderator
250 replies posted 25 likes received 100 solutions authored

Hi,


Thank you for contacting Infineon Technologies.

Q1-->Ans.)  address should be placed on the bus at least before (or equal) CE# low since the address is latched at CE# falling edge. 

Q2-->Ans.) It doesn't describing a specific timing, but those GL-N and GL-S need address latching at CE# falling edge.

Hope it helps.

 

Regards,

Yuvraj 

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KatsumasaH_16
Employee
Employee
10 solutions authored First comment on KBA 50 sign-ins

Hello Kumada-san and Yuvraj-san,

The timing for latching the address when reading in parallel interface products is when CE#=L or when the address changes.

Therefore, it is believed that GL-N datasheet is misstated.

 

Best regards,

Honjo

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Yuvraj
Moderator
Moderator
Moderator
250 replies posted 25 likes received 100 solutions authored

Hi Honjo-San,

"The timing for latching the address when reading in parallel interface products is when CE#=falling edge or when the address changes in page read"

Hope it clarifies your doubt.

 

Regards,

Yuvraj 

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KatsumasaH_16
Employee
Employee
10 solutions authored First comment on KBA 50 sign-ins

Hello Yuvraj-san,

If the address can only be latched with CE# low edge, then continuous address access with CE#=OE#=FIXL is not possible.
P-NOR products, including the GL series, can be used in such a way, so the timing of address latching is not limited to the CE# Low edge.

Best regards,

Honjo

 

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Yuvraj
Moderator
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250 replies posted 25 likes received 100 solutions authored

Hi,

Please find the below comments,

 

  • In case of random read or single word data read = All addresses are latched on the falling edge of CE#.

  • In case of back-to-back read (CS#=FIXL, OE#=toggle) = All addresses are latched on the falling edge of CE# or OE# rising edge (for the next back to back read).

  • and in case of Page read = All addresses are latched on the falling edge of CE# for the first data out, and then the addresses are latched at the A2-A0 transition for the next data out in the page boundary. 

    Hope it helps.

Regards,

Yuvraj 

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KatsumasaH_16
Employee
Employee
10 solutions authored First comment on KBA 50 sign-ins

Hello

If CE#=OE#=FIXL and only the address is changed and read out, if the address can only be latched at CE# low edge, then the data cannot be read out, right?

If the address is switched from CE# low edge to within tCE, if the address can only be latched at CE# low edge, then the data at the correct address cannot be read out, right?

By the way, OE# only controls the output edge, so the address is not latched at the OE edge.
Also, where does "all addresses" mean from and to?

 

Best regards,

Honjo

 

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