Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions
Hi Guys,
May I know the difference between FM24CL64B-G and FM24CL64B-G2TR please?
Not asking about TR, but "2"
What exactly this "2" stands for?
Thank you
Jaroslaw Klofczynski
Regional Sales Manager – Eastern Europe
Mobile: +48 662 828 747
Show LessDear Sir or Madam,
I am using CY15B108QN-40SXI(Blank/T) in our product.
Please provide RoHS Certificate(2011/65/EU, (EU)2015/863) for CY15B108QN-40SXI(Blank/T).
Thanks.
Show LessMay I know CY15B102QN-50SXI read/write performance?
Have any test report for reference?
Is ideally use maximum 50Mhz calculate without overhead will be 50mbit/s?
Show LessI am currently developing a product with the FM25L04B to be used as NVM. We currently have about 56 bytes of data needed to be wrote to the NVM to be saved. Am I able to write all of these bytes one after another after supplying the starting address, or do I need to break it up into two writes since a page only contains 32 bytes?
Show LessHello!
We would like to access CY15B104Q by mmap system call in linux, but result error ENODEV(19): No such device, that means the underlying device not support memory mapping.
Our platform is TI AM64X, RT-linux 5.10, the FRAM has bean found as "/dev/mtd10", and can be read or write, but mmap to "/dev/mtd0" result ENODEV error.
the driver we use: F-RAM/linux-5.4.40-cy-spimem-v20.3.zip at master · Infineon/F-RAM (github.com).
There's a manual doc from cypress noticed that CY15B104QSN support memory mapped access : CYPRESS Memory Mapped Access to SPI F-RAM AN229843 User Guide (manuals.plus)
So maybe we did something wrong, help us, please!
ps:
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We can find CY14B116L-Z45XI parts on website.
https://www.infineon.com/cms/en/product/memories/nvsram-non-volatile-sram/cy14b116l-z45xi/
But ordering information can't find it.
Please help check to provide correct datasheet.
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I want to know the origin of FM24V05-GTR products!Pleasa
Hello,
Does FRAM operation is terminated when SPI master command is interrupted?
For example, Suppose the SPI master asserts CS# low and the clock stops in the middle of a Read or Write command. The maximum clock stop period is about 10 seconds.
If the SPI master then resumes clock oscillation, will the FRAM continue to process this command? Or does timeout processing enter internally and the command is ignored?
CS# stays low until after the clock is stopped and re-started.
MPN: CY15B104Q-PZXI
Best Regards,
Naoaki Morimoto
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