Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions
I have an embedded microprocessor operating as an SPI master with its dedicated SPI bus. The micrprocessor will be running embedded Linux. Do you have a recommendation/example as to how I can write/obtain a kernel driver for the CY14B101P-SFXI or similar nonvolatile serial RAM part?
(I am not referring to configuring the SPI bus in Linux, but rather to write/obtain a driver for a nvSRAM part that makes use of the already existing SPI interface within the kernel.)
Show LessHi
I have a very old circuit using UL634H256 nvSRAM's that has been laid out to use the hardware store and has a 68uf capacitor for Vcap. If I start a software store using a power fail signal I am getting corruption of the EEdata.
If I monitor the Vcap line it never gets disconnected from the 3.3 volt supply so drops quickly. The chip does not get the time to complete. See scope plot. The pink trace falls at the start of the store. Blue is supply and green is Vcap
Is this correct that Vcap only gets disconnected from the supply if a hardware store is going to be performed or every time Vcc drops below Vswitch?
I have tested this on a few boards and some corrupt and some do not but all the signal timings look identical. Any thoughts on why some could be ok.
Colin
Show Lesswe try to use CY14B101P memory with SPI and RTC in AUTOSTORE MODE. on product datasheet at page 3 in table 1 Pin definition the CS pin active the device when is pulled low (GND?? or not connected??). BUT at page 5(of34) on FIgure n.2 Autostore mode the CS is pulled on Vcc with a 10k resistor ( always pulled up when the power in on!!! )
in onother datasheet of product similar ( nvram with RTC but not WITHOUT SPI interface) CY14B101KA at page 4 there is the same drow (figure2 autostore mode) but this thime WE is pulled on wcc with 10 k resistor and this provably is the true configuration!!
on another cypress document the application note AN43593 on page 1 the drow FIgure 1 report a autostore configuration equals then CY14B101KA datasheet..!
another question: we use single chip mode : the HOLD pin is pulled on vcc or gnd for work???
please inform me about the error ! we loss a lot of time for redrow our project!!!
I have a Question about the RWI Inhibit in the Datasheet. Is that an internal Inhibit, or is it controlled by the WE what is the relationship? If WE is not up the first 20 ms, what is the probability of having corrupted data. Can you elaborate more on that relatinoship.
Show LessThe nvSRAM has a specified tHRECALL (Power up RECALL duration) time for boot up / RECALL of data. When user powers up the device, at the end of the tHRECALL period, the device is ready for access. Which means user can perform read/writes. The tHRECALL completion is signaled at the HSB# (Hardware Store Busy) pin and user can start read/write based on HSB# going HIGH in case user is monitoring HSB# pin. HSB# will go HIGH in <= tHRECALL time. Since there is no restriction on what user can do after the part is ready, let us say user performs a write as soon as the part completes the power up RECALL and immediately powers down the part (planned on unplanned power down). The device will perform an AutoStore using the charge from the VCAP pin and it is guaranteed that the AutoStore will be successful under this condition also.
If user now has a capacitor on VCAP pin which is outside the spec, consider a 330uF which is higher than the datasheet spec limit of 180uF max, the capacitor would have charged to a lesser voltage than what would be the level if 180uF was on the pin. This would affect the AutoStore operation completion as described below.
During power down, when the VCC crosses VSWITCH, the power to the internal store circuit switches to the VCAP pin. From then on VCAP charge provides the power required to complete the AutoStore. Assume VSWITCH for the part is 2.4V and the store circuit needs to have a minimum voltage of 2.0V on VCAP to complete the STORE, then the capacitor value should be such that it accumulates enough charge on it to complete the AutoStore operation in tSTORE time (8 ms) while it discharges from 2.4 V to 2.0 V. In the case of higher capacitor, the starting voltage would be lower (since it was charged for the same tHRECALL time from the same internal charging circuit). However it still may accumulate sufficient charges to complete the AutoStore in time which is determined by the value of capacitor and its voltage level above 2V. On the worst case side, assume the capacitor did not even reach 2V because the capacitor value is too high. Then there will be a complete failure of AutoStore. Therefore, the higher value spec for VCAP is specified to guarantee that AutoStore will be successful if it is required to be done as soon as at the end of tHRECALL (= 20ms). If user still needs to use 330uF, user needs to ensure that AutoStore is not going to be required immediately after power up and ensure that there is sufficiently longer time before performing a write operation. (If there is no write operation after a NV operation, there will be no initiation of AutoStore since the NV data is same as the SRAM data). That is, give additional power up time before starting access, say add 20ms more before starting access.
Also note that the typical value mentioned in the datasheet is the minimum cap value with 10% tolerance which will ensure AutoStore will always be completed for any part across PVT (Process, Voltage, Temperature) range. And minimum value is the value net of tolerance (the minimum absolute value) which will ensure that AutoStore is successful across PVT. Please note that the performance of the part is the same if any value of capacitor across the min to max specification is used.
Show LessA nvSRAM memory cell integrates a fast access SRAM cell and a non volatile NV cell in a monolithic die. This cell structure offers the benefit of high performance SRAM access and non volatility of EEPROM/FLASH. In a typical system configuration where the system controller uses external memories for storing its firmware program and data, a Flash memory is used to store the program code and a SRAM is used to store runtime data and variables. During system boot up, the firmware code is first dumped into SRAM from the flash and then executes from SRAM.
S ince the nvSRAM combines SRAM and NV cells, it can potentially replace the combination of SRAM and FLASH with a single memory. After a power cycle, the data stored in NV cells of nvSRAM is available to SRAM after 20 ms (Power up Recall duration) which can be used by the controller for its boot up process. Once boot up process completes, the same SRAM space can be used as data memory for storing run time variables, parameters and scratch pad data. In this used model, the AutoStore feature of nvSRAM must be disabled so that SRAM data is never written back to its NV cell on its own by performing an AutoStore cycle. This will ensure that NV portion always stores the F/W program code. Disabling AutoStore features makes NV memory in nvSRAM as read only memory (ROM). To program the nvSRAM again with a new F/W code and store in its NV cell, on demand Software Store command can be issued which will Store a new code into its NV cell.
The only drawback with this approach is that data is not available in the SRAM for the first 20 ms during power up RECALL duration. It means controller boot up will start only after 20 ms. After 20 ms entire program memory is available in SRAM, whereas in SRAM+Flash combination, controller initially copies code from the program memory (Flash) to data memory (SRAM) on byte by byte basis.
Show LessHi All,
The new serial nvSRAM RTC devices can be used to detect less than a second using its newly added Square Wave generation feature. nvSRAM RTC devices can generate Square wave of frequencies 1 Hz, 512 Hz, 4096 Hz and 32768 Hz on INT pin. This along with RTC time keeping registers can be used to count less than a second.
Regards,
Harsha
Show LessHi,
We currently offer Asynchronous and Serial bus interfaces on our nvSRAM. What do you think are the most useful Synchronous interfaces for the future for our nonvolatile products?
Thanks
Ravi
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