Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions
We are looking for Linux drivers for this F-RAM: FM25W256-G.
We're new to developing on these and I'm also wondering if we install drivers the FRAM will show up in the system as a type of "hard disk" that we can mount and then transfer files in the traditional way with "scp" command.
Or is this more barebones than that and we need to develop the drivers and software to store the data ourselves? If so does anyone have any useful resources on how to get started?Show Less
This FRAM and FPGA are connected, and it is only a short time until the configuration of the FPGA is completed → the board power is turned on,
The voltage is indeterminate. (Only CE1 and CE2 are pulled up, so it is HIGH.) ）
For WE, OE, address, and data, is there any problem even if the voltage is indeterminate?Show Less
Hello, I have found one of my devices to show data correction on a very large scale and we are wondering if environmental exposure of some type could have caused the large corruption of data. We see at the very least a 4kB block of corrupted data.
So, could I expect the following environmental sources as the cause of my data corruption:
- Excess dwell and excees reflow temperature : I have the reflow profile available to us but are these devices more vulnerable than others to excess heat or dwell during reflow and does this cause data corruption ?
- ESD exposure : I would expect that ESD environments would cause I/O to stop working first and that has not occured. The device functions properly but develops data corruption
- Voltage supply rail ramp up or ramp down : could the speed of ramp up or down of the 3.3V rail cause the device to have corrupted data.
- Could parasitic powering via I/O pins prior to 3.3V rail cause the device to lose have corrupted data ?
- Radiated EMC susceptability : Do these devices (FRAM technology) have more vulnerabilities to EMC radiated suscepatbility than other technologies ?
I am running with SCLK at 25MHz (device max is 40MHz) and I am using a single write command stream to write the entire device. This has been show to work fine over numerous device write and read testings of numerous power cycles. We have been using this configuration for over two years and have seen this occur on only one (1) board (1 device / board) so far.
The FPGA write controller code has the device fully unlocked and does all of the normal write operations prior to the Write action. We can re-write the device but the corruption seems to re-appear after a time period. We do not know all of the environmental exposure sources this unit is seeing at this time.
Can you offer any assistance about what could be causing this corruption of data in this CY15B104Q-SXI device?
Also, I have checked the 3.3V power rail and it ramps up monotonically from 0 to 3.3V in 1.5 millisec. Nice and clean. The FRAM SPI interface is connected to a Xilinx FPGA which has its pins tristated (high Z) during and after power up of the 3.3V rail and while the device is being configured for which takes about 300 milliseconds. So there is a huge delay between when the power monotonically comes up and the device is first accessed during which the time the SPI pins are high Z.
- We have a pullup to 3.3V on the CS_n, Hold_n, and WP_n lines (10k)
- The 3.3V power rail is very clean with less than 10mV rms noise
- The tPU spec is easily met since the device pins are in High Z while the power is ramped (in 1.5msec) monotonically and then is static for the next 300msec while the device running the CY15B104Q-SXI's SPI interface is being configured.
Thanks, TomShow Less
Please tell me about fSCL as described in the AC Switching Characteristics on datasheet page11.
Datasheet shows three parameters: Max=0.1MHz, Max=0.4MHz, and Max=1.0MHz.
Should I refer to the parameters that are in the range of fSCL to be input to the IC?
For example, if input fSCL=300kHz, refer to the parameter of fSCL_max=0.4MHz.
If input fSCL=800kHz, Refer to the parameter of fSCL_max=1.0MHz.
Is it correct?
There are standard and custom packages in the CY14V101 series, but what is the difference?
Dear Sir/ Ma'am
Embedded Hardware Engg.
I patched the linux-5.4.40-cy-spimem.patch to TI provided SDK.
And I modified the device tree like below,
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
ti,pindir-d0-out-d1-in = <1>;
compatible = "cy-spimem", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
#data-size = <16>;
But the spi speed is not 40Mhz as expected. Please help to point out how to set the spi speed in device tree for FRAM?
Has the FM25V02A or similar FRAM device been tested for EMI environments like RS103 up to or beyond levels of 20,000 V/m?
We are experiencing issues where even though the system is configured to not write to the device, the first few addresses (0,1,2,3) are changing value when exposed to a radiated field at high levels.Show Less
Current Infineon website have something wrong of CY15E064J-SXE data.
The link datasheet download is CY15E064J-SXA not CY15E064J-SXE.
And this parts support 5V, but parts sorting at 3.3V.
So, please help provide CY15E064J-SXE datasheet for reference.