Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions
Hello! We got a batch of CY15B104Q-SXI. The screen print on the top is CY15B104QS, and the reading device ID is: 7F7F7F7F7F7FC226A8. I think it should be 7F7F7F7F7F7F7FC22608 in the data sheet. Please help confirm: 1. Is the screen printing CY15B104QS corresponding to CY15B104Q-SXI? 2. Is the model corresponding to 7F7F7F7F7F7FC226A8 CY15B104Q-SXI? Thank you!
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E9%9D%9E%E6%98%93%E5%A4%B1%E6%80%A7RAM-F-RAM-NVSRAM/%E5%85%B3%E4%BA%8ECY15B104Q-SXI/td-p/654957
Show LessHello,
I have a question regarding the part FM22L16-55-TG (256K x 16 FRam Parallel memory).
We are in the process of connecting this with a micro processor and want to have a data bus of 16bits, but do not want to limit reads and writes (more on the writes) to also always have to be 16bits (desire 8 bit reads and writes as well)
Our plan is to connect the UB and LB lines to the micro processors byte lane output pins (STM part, NBL lines of the Flex memory controller) such that our byte writes do not overwrite other data (force 16 bits)
Our concern is what happens if during init or before the micro is up, the UB and LB lines of the memory get driven in the same direction (both high or both low)? Is there any combination of these pins that could damage the chip?
Thanks,
-mike
Show LessWhat is the capacitor value for NvSRAM in CY14V101LA-BA25XIT?
Hi, can anybody explain this behaviour to me please (see scope capture)?
I write 3 bytes to memory like this:
Chip select low
Send WREN (0x06), WRITE (0x02), high addr (0x61) low addr (0x5E), data (0x0B, 0x81, 0x51)
Chip select high (some 20us or so)
Chip select low
Send READ (0x03), high addr (0x61) low addr (0x5E), dummy data (0x00, 0x00,0x00)
Returned data comes back in the order 0x51, 0x81, 0x0B
Why does the data come back in reverse order when I start from the same address?
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When using CY15B102Q-SXET originally produced by your company, we found that the side of the pin of CY15B102Q-SXET(SOIC-8 package) does not tin, so we need to increase the soldering iron temperature and welding time to repair the solder joint of the pin. But this method will cause hidden trouble to the quality of the chip.
Subsequently, our company transferred ten CY15B102Q-SXET from the warehouse. Before any treatment, all the chip pins showed a dull and dull state; After operation according to method 2003.1 weldability of "GJB548B-2005 Test Method for Microelectronic Devices", all chip pins show bright coating, continuous tin surface, full coating and good tin from the front view; When all the chips were raised to observe the side of the pins, it was found that there were pitting points, no wetting of the coating and discontinuous tinning on the side of the pins.
We believe that this situation is not the cause of preservation, but the quality of the device reference script. If it is a preservation problem, it should be that the entire pin is not oxidized on the tin; However, after the test, the pin face, the front heel, the back heel to follow the tin are particularly good, only the two sides of the pin on the tin effect is particularly poor.
Could you tell us how we should handle this situation? Looking forward to your reply very much.
Normally, I would expect to see the Seal Date earlier than the Mark Date since the packaging of the component in its final form precedes the Top Marking.
Is it ever possible to find a Seal Date that is after the Mark Date?
Show LessI'm not getting data returned back from the FRAM chip when I send a read request or RDID request.
I'm not sure what I'm doing wrong.
I've attached my wave forms of HOLD_N, CS_N, serial data out of FRAM, serial data into FRAM, CLK, WP_N.
Any help would be appreciated.
Show LessThe website lists the reflow temperature as 220°, but the data sheet lists it as 260°. Is 260° correct?
CY14B101J2-SXIT
https://www.infineon.com/cms/jp/product/memories/nvsram-non-volatile-sram/cy14b101j2-sxit/
データシート
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