Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions
您好!
我的机器人板卡上使用了一颗FM22LD16, 板卡上方有一个电机,在此应用场景下,铁电容易读写错误,拿到实验室下,读写错误现象消失,请问是否存在电机对铁电的影响?谢谢
Hi Sir,
An FM22LD16 is used on the board card of my robot, and there is a motor on the top of the board card. In this application scenario, f-ram is easy to make reading and writing errors. When taken to the laboratory, the phenomenon of reading and writing errors disappears. Is there any influence of motor to F-ram?
thank you
Show LessHi all,
I'm looking for some information about the SEU/MBU rate of the NV RAM FM28V100-TG.
I found an application note, AN15979, describing that for NV RAM, MBU is "virtually impossible" due to the way the memory is architected.But this document is not referenced in the Application Note of the Memory (cf. page https://www.cypress.com/part/fm28v100-tg ) so I would like to be sure that the Application note is applicable to this memory
Concerning SEU, I do not found information allowing me to calculate the rate. If there is somewhere some test results, or some data about the FM28V100-TG cross section, it would be extremely usefull !
In a general way, any information on the subject will be interesting
Thanks,
Romain
Show LessHi,
Could you please provide the IBIS model for CY15B102N-ZS60XAT.
We planning replacing FM28V202A with CY15B102N-ZS60XAT in our design. Is the performance characteristics of both the devices are same?
Show LessI got a question when I try to put a production test plan for FM25V20A FRAM. Our primary use for FRAM is to write in log files and pull to an external device. We are utilizing every cell in FRAM. If I want to test write and read to random memory address on each page of memory, the firmware implementation will be intensive. We have turn off the fire system (in other word, shut off the normal operating system) to do this. So I am seeking advice on how to test FRAM in production environment. Does it have a built-in error correction/check if something is wrong while writing to a memory address? Or, does it have certain failure mode that is necessary to check out before assembly?
Show LessAs the datasheet "001-84499_FM25V10_1_Mbit_128K_X_8_Serial_SPI_F_RAM.pdf" describes :
The read access is as on the attached picture.
So Bit 23 (the 24th) is the last bit written, on the rising slope of SCK. The 1st read data bit D7 is available upon the falling slope of the same SCK pulse, which is somewhat unusual. Especially since the last bit read (D0) is available on the falling 6th read-SCK. The 7th read-SCK is for nothing.
In my opinion, SO line should be shifted by one SCK to the right. Such that the bit D7 is available after the falling 0th read-SCK. And eventuall the last bit, D0, is available after the falling read-SCK7.
Please confirm and adjust the datasheet.
Dear Sirs,
I have just started to use these FRAM memories. My test software for writing and reading is working 99% of the time.Occasionally I get a corrupted read immediately after power up. The memory contents is not corrupted as a further power cycle gives the correct results.
I have noticed that the power up conditions are specified in the data sheet. There is no problem with tPU, as my first read is at least 100ms after Vdd is stable. However there may be a problem with tVR. I have measured the rise time from 0V to 2V as 95us/V. My Vdd fall time is much slower than the spec, being 2.7ms/V.
Could you please explain the significance of these specifications. The memories are part of a complex design, and it would be difficult to change the Vdd rise and fall times without powering the memories from a special supply.
Is there a software solution to reset the memories after power up?
regards
Cosmo Little
Show LessSometimes it is useful to have a simple and easy-to-use development & test platform at hand. The popular Raspberry Pi platform meets these needs. It is inexpensive, popular and easy to set up.
The SPI controller that is integrated into the Pi's Broadcom SOCs supports single I/O SPI with frequencies of up to 125 MHz. Two chip selects are available on the 40-pin expansion connector. DMA from and to SPI devices is supported as well. Supply and I/O voltages are normally 3.3V.
The following instructions summarize how to set up the Cypress SPI Memories Driver for Linux on a Raspberry Pi.
1. Kernel Compilation
Pick a suitable Linux kernel (e.g. branch rpi-4.14.y) and follow the official kernel build instructions. Apply the Cypress SPI Driver patch to the kernel tree and enable CONFIG_MTD_CY_SPIMEM and CONFIG_MTD_CY_HAL_GENERIC in the configuration menu.
2. Device Tree Settings
Edit the device tree file of your Raspberry Pi (e.g. arch/arm/boot/dts/bcm2710-rpi-3-b.dts for the Raspberry Pi 3 Model B). In the SPI device section, reduce the SPI clock frequency from 125 MHz to e.g. 25 MHz and change the driver from “spidev” to “cy-spimem”) as highlighted in the following dts snapshot:
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
spidev0: spidev@0{
compatible = "cy-spimem";
reg = <0>; /* CE0 */
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <25000000>;
};
3. Hardware Setup
Attach a SPI memory device to the SPI pins of the 40-pin expansion connector.
4. Boot the System
If everything has been set up correctly, the SPI memory device is probed and reported in the kernel boot log
Found Cypress CY15B104Q (F-RAM)
and registered as a MTD device
# cat /proc/mtd
dev: size erasesize name
mtd0: 00080000 00000200 "CY15B104Q"
Afterwards, it can be accessed via standard Linux tools.
Show LessDear Cypress team,
I wonder if there is any compatible driver for this device at the space of U-Boot,
and U-Boot is release of 2016.07 on ARM platform.
Thanks.
Walter
Show Less