we are having issues with BP1 and/or BP0 being set seemingly random after a write to the FRAM occured. We have one board design with said FRAM chip and it occures on all of the tested boards to date (around 5). We checked the supply voltage and SPI and everything looks good to us. We also checked the SPI signals for noise, but this also looks good.
This shows two write sequences that consist of checking for the block protection bits followed by the write to the FRAM. After the first write both block protection bits are set and we cannot figure out why. The block protection bits are set randomly after any write. So not necessarily after the first. We have 4 writes every few seconds.
Supply was measured close to the FRAM
We tried hard to find an issue in the supply voltage or communication with the FRAM. Is there something obvious we missed? Could this be a result of too much heat during board production? We have yet to check if the write operation before the protection bits are set were successful.
Attached you can find a .psdata file that you can open with the free Picoscope 6 application to have a close look a the signals.Show Less
HI dear friends,
Pls advise what are the differences between "10ZI" and "10ZXI" parts.
Are the "10ZI" parts not Pb-free?
But there is square mark (Pb-Free mark) on the parts.
Or is it normal? Pls help.
Best regards and thank U.
I'm working with CY15B116QSN device using 002-26981 preliminary datasheet.
I've developed a VHDL FRAM access engine and now i'm simulating the FRAM behaviour. I'm using QSPI access @ 67,5MHz.
In the table AC switching caracteristic of device CY15B116QSN i'have seen we need to meet tcs chip deselect time.
that is described as: "the minimum chip deselect (CS_HIGH) time before the new command cycle starts in a specific SPI mode. This parameter ensures that previous operation is successfully completed before the host start a new command cycle"
i follow this spec during Register access to setup the CR1, CR2 and CR5 register.
My question is:
Have i to respect it if i would access to Memory content using only the commands:
- 0x02 (memory write) and
- 0x03 (memory read) ?
If yes which time i have to follow ? 110 ns ?
Can Cypress provide the projected maximum density pin connections for memory packages to allow customers to attach higher density parts? Higher density parts may be required when customers run out of memory or if the lower density parts are EOL'd?
- 8-Mbit CY14B108L/N both x8 in 44-TSOP and x16 in 54-TSOP Pin Diagrams on page 3 of the data sheet @ https://www.cypress.com/file/43046/download show expansion connection to next higher 16-Mbit density.
- 16-Mbit CYB116L/L only x8 in 44-TSOP Pin Diagram on page 4 of the data sheet @ https://www.cypress.com/file/46601/download shows expansion to next higher 32-Mbit density.
I did find a competitor's pin diagram for a 32-Mbit x16 RAM in 54-TSOP that shows the addition of ADDR(20) to pin 1.
Will Cypress follow this competitor who has published a 32-Mbit RAM pin-out?
Will ADDR(21) be assigned to one of pins 25-30 for 64-Mbit x16 RAM?
Will the 54-TSOP II package support higher density RAM? If so, where will ADDR(22-26) be assigned?
Thanks for your support.
Can anyone confirm if the top markings of this component are correct for the component. top marking documents are not helping us to identify it is the correct part.
Marking is 2 lines as below
Cypress doesn't provide serial F-RAM part-numbers working in the -55/+125°C range. The widest range available is the automotive range (-40/+125°C).
Is it something impossible with the F-RAM technology to work at -55°C?
Or would it be possible to have chips working in the -55/+125°C range using an uspscreening process?
Thank you.Show Less
Autostore: VCC < VswitchとなりStore処理が開始されたとき、
・Store処理が完了する前に、VCC > Vswitchとなった場合の内部挙動はどうなりますか。
・VCC > Vswitchとなり、RECALL処理が開始されたとき、
tHRECALLの時間を待たずに、VCC < Vswitchとなった場合の内部挙動はどうなりますか。
Can anyone direct me to a chip programmer supplier that can read/write to the CY14B256LA?