We will support to design in CY14B101LA-SZ45XIT NVRAM.
Have we NVRAM layout guideline to conform it?
Ex:Impedance, line width/line interval space/line length information
Is there an IBIS model available for the radiation tolerant FRAM CYRS15B102Q? Or is it just equivalent to the CY15B104Q?Show Less
Which NVSRAM interface suitable on GSPI (Generic SPI)?
I see other posts asking if the CY14E256LA-SZ25XI was obsolete and Infineon states full production. Digi-key and Mouser list as Obsolete. Digi-key sent me the attached list (PD220902A) of Product Discontinuation. It lists the CY14E256LA-SZ25XI as being obsolete with the 3.3V chip (CY14B256LA-SP25XI) as the Next Best Alternative Part.
Is this list of discontinued Memory Products correct?
How was this list generated if the part had not been Discontinued.
Should I make a case to redesign all our assemblies or are these parts not be in Discontinued?
Soft Error Rate discussion on NvRAM in thread from 10/16/2018 06:00PM provided a Report file to the discussion initiator. Are similar SEU/SEL report files available on NvRAM parts STK14C88-3NF35I and CY14B256LA-SZ25XIT?
In the Write operation, if / WE is asserted and then negated earlier than the Min value of tpwe,
Is the content of SRAM at the address undefined? Or does the previous value remain?
If it is undefined, if the power is turned off and then turned on in that state, the SRAM → nvSRAM store operation (@power off) will be performed as an indefinite value.
Does nvSRAM → SRAM recall operation (@ power ON) and nvSRAM operates with an undefined value?Show Less
we have a prototyping board equipped with fram (part number cy15v108qn-20lpxi). The mcu controller is ti's cc2640r2f. I have tried both gpio bitbang and spi hardware to read status register. The results are the same. the first byte, 0x05, is issued from mcu and the fram chip did respond a byte, an 0x0c, which is an illegal value according to manual, since the bit 6 is not set. Also bit 2 & bit 3 is not the default value (supposed to be 0).
Attached are waveforms I photoed from my osilloscope (sorry that i have only a low-cost, dual-channel one at hand, but I think it is enough for the job). One shows the first byte is 0x05, correctly issued from the host. The other shows the second byte replied from fram. The wave form looks OK but the value 0x0c is incorrect according to datasheet.
Also, I have tried to read device id (0x9f) and unique id (0x4c). Both commands returned only zeros, which seems to be incorrect.
any good explanations for the problems? or any timing error in wave forms? or the chips are broken? shed me some light.
I am trying to read the Device ID from a CY15B104QN-50SXA chip and am getting out 0x402CC27F7F7F7F7F7F, which is the LSB to MSB read of the actual device ID listed in the datasheet, 0x7F7F7F7F7F7FC22C40. The datasheet claims the chip should read it out MSB to LSB, is there a reason this wouldn't be the case? Are other read/write operations affected as well?Show Less
A customer tells me Cypress Part Number CY14E256LA-SZ45XI is obsolete.
The Infineon website says it's 'active and preferred'.
Infineon support says they 'do not support Cypress components yet '.
Is Cypress Part Number CY14E256LA-SZ45XI obsolete or is it still available in the 32-pin SOIC?Show Less