As the datasheet "001-84499_FM25V10_1_Mbit_128K_X_8_Serial_SPI_F_RAM.pdf" describes :

The read access is as on the attached picture.

So Bit 23 (the 24th) is the last bit written, on the rising slope of SCK. The 1st read data bit D7 is available upon the falling slope of the same SCK pulse, which is somewhat unusual. Especially since the last bit read (D0) is available  on the falling 6th read-SCK. The 7th read-SCK is for nothing.

In my opinion, SO line should be shifted by one SCK to the right. Such that the bit D7 is available after the falling 0th read-SCK. And eventuall the last bit, D0, is available after the falling read-SCK7.

Please confirm and adjust the datasheet.

Dear Sirs,

  I have just started to use these FRAM memories. My test software for writing and reading is working 99% of the time.Occasionally I get a corrupted read immediately after power up. The memory contents is not corrupted as a further power cycle gives the correct results.

  I have noticed that the power up conditions are specified in the data sheet. There is no problem with tPU, as my first read is at least 100ms after Vdd is stable. However there may be a problem with tVR. I have measured the rise time from 0V to 2V as 95us/V.   My Vdd fall time is much slower than the spec, being 2.7ms/V.

Could you please explain the significance of these specifications. The memories are part of a complex design, and it would be difficult to change the Vdd rise and fall times without powering the memories from a special supply.

Is there a software solution to reset the memories after power up?

regards

Cosmo Little

Dear Cypress team,

I wonder if there is any compatible driver for this device at the space of U-Boot,

and U-Boot is release of 2016.07 on ARM platform.

Thanks.

Walter

Hello community,

is there any Chance to replace a 5V SRAM 1to1 with the FM28V100 without the levelshifting things?

If i will reduce the circuit Voltage for the FRAM to 4V (ZDIODE ?) ?

In the Datasheets Maximum Ratings is stated as follows:

VDD relative toVSS -1V to 4.5V

and Input Voltage -1V to 4.5V and Vin<VDD+1V

Thank you in Advance for your answers.

Michael

Hello,

What is the technology size for the FRAM CY15B102Q?  Also, has this part (or similar FRAM parts) been tested for Single Event Upsets and Single Event Latchup?  If so, what would be the associated SER?

Hi,

We are currently experiencing high rates of data corruption in a CY15B104Q-LHXI device on our design.  We see corruption occur only when we write at a high temperature (up to +85C), power cycle and then read at low temperature (down to -40C).

Corruption appears to be at random locations in the device, and we see bits transition in both directions. The failure rate increases with the delta in temperature between write/read cycles.

We're currently investigating, and have started looking for potential reasons for the corruption.  We have a come across a few questions, would it be possible for one of the Cypress folks to take a look?

1. We find that if we replace the part with CY15Q102Q-S, OR FM25V20A the corruption does not occur. Are there any significant architectural differences between the 4Mb part and these 2Mb parts which may be causing the effect?

2. We have connected the centre pad to 0V on our design, although I noticed a note in the datasheet instructing it to be left floating. What are the implications of connecting this pad to ground?  Is this is possible reason for the corruption?

3. I have been looking at App notes AN304 and AN302, which give recommendations about holding chip select inactive during power transitions, and we are currently investigating this. However, I noticed that AN302 is marked as obsolete. What is the reason for that?  Is there any information in the note which is incorrect?

I'd be very interested to hear your thoughts, and know if you can suggest any reasons for the corruption.

Many thanks,

Bryan.

I am using a CY14B101PA, NvRAM/RTC device.

I remove the RTC backup battery. After powerup, I see the OSCF and BPF asserted. I clear them and wait 10 msec. I see the OSCF remain at 0, which makes sense. However, the BPF flag remains 0 even though there is no RTC battery.

Is this expected behavior?

Thank you for any input.