Non Volatile RAM (F-RAM & NVSRAM)

Hey guys, I see FM24C16-P(8 pin DIP) is obsolete on digikey/mouser. I found an alternative FM24C16C-G which is a 8 pin soic . I just wanted to confirm except for the package type dfiference(SOIC vs DIP), rest all is same for both the chips. 

Hello, 

I am in need of a IC FRAM 8Mb SPI 20MHz 8GQFN memory. I planned on using the Infineon part #CY15B108QI-20LPXI, but it is out of stock everywhere. I am having trouble finding a replacement from Infineon or other competitors. I already need it to be able to operate in high temperatures (around 120C). If anyone knows of a replacement or has any recommendations, that would be highly appreciated!

Thanks!

We have seen the following situtation when using a CY15B104Q-SXI which is accessed by an FPGA on a board with stable power up timing. After a an operation which writes ALL of the locations with a three (3) pass method with 0x00, 0xFF, and 0xAA (the FRAM will be left with ALL locations at 0xAA) we have found errors in the data read from the FRAM. It appears that the data read out by the FPGA from the device into a Block RAM buffer inside the FPGA is incorrect. We have the actual device in hand. Also, during debug of our code it was possible that WRITE accesses ocurred at a location past 524,287 (rollover).

Here are some details of the operation :
The power up code sets the WRDI to have BP(1:0) set to "00" : No Write protection

The WRITE operations are all performed with a WREN command and then a block WRITE with the entire memory length written in one block. There are no individual WREN WRITE operations at a single address. The FRAM is written with one WREN/WRITE of the entire 512K size with same data witten in three passes : 0x00, 0xFF, and last 0xAA.

The READ operations which _export_the_entire_memory_to_a_host_PC_over_a_UART port from the FPGA are individual READ operations at a single address and the output looks correct.

The READ operations which _load_a_portion_of_the_FRAM memory to the BRAM inside the FPGA are block READ operations from an offset address to a small range of less than 16K Bytes. When we export the contents of the BRAM (loaded from FRAM) we see corruption in the form of the AA bytes occupying a large section of the expeted data, followed by the remainder of the expected data. THe BRAM is loaded with the fast read option.

Now, we have shown that when we BLOCK WRITE using the three (3) method (again, all are BLOCK WRITEs of exact length of the full FRAM size starting from addr 0 and ending at 524,287) with write timing obeyed (CS high duration between Block Write operations at 25MHz SPI timing) gives incorrect READ data from the BRAM buffer to the host. We can see that some swaths (contiguous regions) still have incorrct data in them from a previous pass.

However, we have found out that when we change the operation of the FRAM three pass to finish with 0x00 (00's left in entire FRAM space) the READ operations are performed correctly for all locations.

FRAMのシミュレーションモデルを使用してQuartus16.1環境にてコンパイルを実施したところ、以下のエラーメッセージとなりました。
Error (10106): Verilog HDL Loop error at FM28V202.v(161): loop must terminate within 5000 iterations
どのように対処すればよいかアドバイスをいただけないでしょうか。

1)FRAMシミュレーションモデルの実装について
Qsysで用意した「Generic Tri-State Controller」の「readdata、writedata、read、write、chipselect、address」信号を同じくQsys上の「Tri-State Conduit Bridge」を介して、Top階層に配置したFRAMシミュレーションモデルに接続しています。

FRAMシミュレーションモデルの「UB、LB」はGND接続しています。

ただエラーメッセージを見る限り、FRAMシミュレーションモデル内のループ回数の記述が違反しているとなっているので、
FRAMシミュレーションモデル側の記述の問題であるように見えました。

「Analysis&Synthesis」のエラー発生ログ
添付 ERR_Message_Log1.txt

2)config.v(124) `define initMemFile "init.dat" をコメントアウトし、
初期化時init.datを読み込むように変更しましたが同様に「Analysis&Synthesis」にてエラーが発生しています。

「Analysis&Synthesis」のエラー発生ログ
添付 ERR_Message_Log2.txt

MPN FM28V202A-TG
https://www.infineon.com/cms/en/search.html#!term=FM28V202&view=all

よろしくお願いいたします。