Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions

Current Infineon website have something wrong of CY15E064J-SXE data.

https://www.infineon.com/cms/en/product/memories/f-ram-ferroelectric-ram/cy15e064j-sxe/

The link datasheet download is CY15E064J-SXA not CY15E064J-SXE.

https://www.infineon.com/cms/en/product/memories/f-ram-ferroelectric-ram/?filterValues=~(233~(~%27I2C)~1009_nom~(~8000)~284_max~(~125))&visibleColumnIds=name,orderOnline,551,1009_nom,233,286_min,286_max,413,packageName,284_min,284_max,422_nom,246,1056,253_nom#!products

And this parts support 5V, but parts sorting at 3.3V.

So, please help provide CY15E064J-SXE datasheet for reference.

Thanks,

Mitchell

We've been using your CY14E256LA-SZ45XI in our PCB designs for many years now and it's been a great and reliable part for us. Unfortunately, we've gotten the same bad news that others in this forum have posted about in that the part is going obsolete and there are last time buys being accepted up until Dec of 2022.

We presently use it with a 5V 8051 microcontroller.

Do you have any recommendations for a replacement part, even if it's not pin compatible?

We see many parts out there, but most are 3.3V compliant.

We thought that your "FM1808B-SG" FRAM would effectively be a drop in replacement (with a minor board layout change). However, a further inspection of its data sheet indicates that each memory access must have a separate strobe of the chip enable line.

Looking at an analyzer capture of our present design, our 8051 will keep the chip enable low (top row signal) for consecutive writes to different memory locations:

Based on this plot and your FRAM data sheet, I assume I'm reading it correctly at that the "FM1808B-SG" would not be compliant with our 8051 memory control timing?

We are using CY14B116N-Z30XI nvsram in a pcmcia memory card.
The CY14B116N-Z30XI connects to a AGLP125 which generates the control signals for the nvsram and the pcmcia bus. The WE pin is pulled up by a 10k resistor and there's a 22uf cap on the VCAP pin. When the card is power cycled some cards unintentionally change data in the nvsram without any writes from the processor. The datasheet for the CY14B116N-Z30XI describes the autostore function and how to disable it using software read command sequences.  The FPGA was updated to drive HSB high by default instead of just during read/write operations, with only a weak pull-up in the nvsram otherwise. Does it make sense that driving HSB high by default would eliminate corruption in the nvsram since HSB is active low and why? If this this change doesn't fully solve the problem we could look at creating a FSM in the FPGA to create the autostore disable sequence.