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Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions

Cosmo_Little
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Sirs,

I have been chasing an intermittent write problem with the CY15B104Q-SPI

1/- Hardware. 4off memories are connected to SPI2 on the dsPIC33E512GM304 micro. The SPI is dedicated to the memories and is not used by any other devices. The SPI clock rate is 12.5MHz. 4 latched chip selects are provided to each memory.

2/- software. The memories are labelled A,B,C,D. The data words are 32 bit. The system writes data to the memories as follows:   a) chip select memory A. Send write enable command. Send write command.

                   b)  send 32 data bits with 32 clocks (one data word)

  The memory remains chip selected until the next memory word is written.

  After  131,008 data words ( the top 256 bytes of each memory are not used for data) memory A  chip select is set high and the sequence is repeated for memory B.

The time between data word writes varies between 100us and 10 seconds depending on the operation of the system.

 

3/ Problem.  With   word write intervals of 100us to 10ms, no errors occur . With write intervals of 100ms or greater random bit errors occur. There may be one or more bits in the 32bit word incorrectly complemented. The words preceding and following the incorrect word are always correct.

  See attached data plot for an example. The boundaries where the memory is switched are at 131007,262014, and 393023 words.  NOTE THAT MEMORY D SHOWS MORE GLITCHES THAN THE OTHERS.

I have isolated one incorrect write as an example. Note two bits are complemented from the correct values.

Note that I have replaced real data with a sawtooth for clarity.

As an additional check, the CY15B104Q memories were replaced with 23LC1024-I/SN volatile serial RAM. No write glitches were observed. This seems to indicate that the SPI is working correctly.

 

4/-   Hypothesis.. There is a failure mechanism in the F-RAM memories which occurs if the interval between writes ( with the memory in write mode and chip selected) becomes too long.  The fact that one memory shows many more write failures than the other three seems to indicate that the problem is sample dependent.

 

Please review this as quickly as possible. Note we used CY15B104Q rather than CY15B104QN.  Have there been any changes to the chip design?

regards

Cosmo Little

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8 Replies
DesaiShubham
Moderator
Moderator
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50 sign-ins 25 replies posted First like received

Hi @Cosmo_Little ,

 

Please answer a few of my queries that would help us to debug

 

> Could you please let us know when you observed this issue? Have you observed it recently or from the very start?

>Could you please let us know how many devices you are observing this failure?

> Could you please share the read and write waveforms with us

>Could you please share the power-up and power-down waveforms with us

> Also, please elaborate on the sequence you are following for writing and reading.

 

Thanks,

Shubham

 

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Dear Shubham

1/- This is a modification to a well established product that uses 4 off Microchip 23LC1024  serial volatile RAM. We have upgraded to use 4off CY15B104Q. The problem arose when testing the prototype. We have only tested 4 memories.

2/- Attached write waveforms. This is the sequence for each data word (32bits) write showing two successive writes of 16 bits.

3/- All tests of the memories with different firmware routines pass successfully. We have a test routine that writes a full checker board pattern to each memory , and tests for stuck or inverted bits. We also have read the memory with different firmware routines, so I am sure the problem is a write failure not a read failure.

4/- I emphasize the fact that all tests made with less than 10ms between writes with the memory chip selected do not show any write errors. Errors only occur if the time between writes is greater than 100ms.

5//- Before the data writing starts, a considerable amount of housekeeping data is written to the upper 256 bytes of each memory. These writes never fail.

6/- Please indicate the changes between the CY15B104Q and the CY15B104QN

 

regards

 

Cosmo Little

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Cosmo_Little
Level 1
Level 1
5 replies posted 5 sign-ins Welcome!

Dear Shubham

Attached power up waveforms. Trace 1 is 12V power. Trace 2 is Vdd, and trace 3 is the memory chip select.

This is with a fast rise time for the 12V power. Normally the 12V rise time will be quite slow, with a longer Vdd rise time

regards

 

Cosmo Little

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DesaiShubham
Moderator
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Moderator
50 sign-ins 25 replies posted First like received

Hi @Cosmo_Little ,

 

Please go through the below comment for your question.

Q>Please indicate the changes between the CY15B104Q and the CY15B104QN

 

Ans : Please go though the application note, which explains difference between both the devices. Only pin 7 of the CY15B104QN is DNU but application note says its RESET and for more clarification for this pin 7 you can refer the latest datasheet.

 

Link for Application Note: https://www.infineon.com/dgdl/Infineon-AN221988_Migrating_from_CY15B104Q_to_CY15B104QN-ApplicationNo...

 

 

 

Please provide response for the follow-up questions

 

Q1>Confirm the sequence you are performing for

Pass test sequence:

  1. Chip select low
  2. send WREN
  3. Chip select high
  4. Chip select low
  5. Send WRITE with address and 32 bits to be written keeping CS low
  6. keep CS low
  7. wait for 100 us to 10 ms in chip select low state before the next data word (32bit) sent on the bus
  8. Again repeat steps 6 to 7 for the rest of the data to be written?

 

Fail test sequence:   

  1. Chip select low
  2. send WREN
  3. Chip select high
  4. Chip select low
  5. Send WRITE with address and 32 bits to be written keeping CS low
  6. keep CS low
  7. wait for 100 ms or greater in chip select low state before the next data word (32bit) sent on the bus
  8. Again repeat steps 6 to 7 for the rest of the data to be written?

 

 

 

 

Q> Could please only mount one device on the system (other three devices not mounted) and test the device if he is able to observe the failure. We are Trying to see if shared bus is causing any issue like glitches

 

Q>Please provide write waveform with correct nomenclature (Provide Naming On the Line)?

 

Q>Could you Please provide the high-resolution waveform at the Ramp-Up stage?

 

Q> Could you please provide schematic?

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Dear Shubham

To reply to your further questions:

1/- I have only tried CY15B104Q.  Hold pin is connected to Vdd. Differences between this and suffix N variant are noted. This should not change the schematic as new reset pin will be connected to Vdd.

2/- Your question  Q1 sequences are correct. Note I have also tested at 20ms and 50ms between data writes. At 20ms no errors. At 50ms memory D showed a few errors. ( see attachment)

3/- I am reluctant to remove devices as these were hard to install as the SO package is wider than the standard SO, so it was quite difficult to solder in the devices. Our next batch of PCBs have a modified footprint, however these have not yet been assembled. Please see schematic, there are only these 4 memories on SPI2

4/- Attached new write waveforms. Ch1 (yellow) is clock. Ch2(red) is data. Ch3 (blue) is chip select.  ChA (orange)is clock expansion. ChB(white) is data expansion. Note data changes on negative clock edges.

5/-  Attached new power up waveforms. Ch1 is 12V power. Ch 2 is Vdd. Ch3 is chip select. Note Vdd rise time is 77us/V

which is within spec.

 

6/- Part schematic attached. Memories use SPI2 ( sck, sdo, sdi) and 4 latched chip selects.

 

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DesaiShubham
Moderator
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50 sign-ins 25 replies posted First like received

Hi @Cosmo_Little ,

 

Thank you for your response.

>Could you please mention volume for CY15B104Q-SXI you have? 
>Could please provide TOP marking?
>Could you please confirm if you are holding the CS low for more than 10ms, with clock gating, is an application requirement or part of your stress testing only?

 

Thanks,

Shubham

 

 

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Dear Shubham.

1/-  Low volume, perhaps 40 units a year

2/- See photo

3/  Our firmware is similar to that used for the volatile RAM option, which has never shown any problems. We essentially added the write enable step for use with the FRAM. The data is acquired over time scales from seconds to days, at different acquisition rates. The method of holding the chip select low for the entire data acquisition time was the simplest method of using the memories. Obviously I could deselect the memory after the data write. However I would then need to go through the write enable/address/write sequence before each new data write. In addition I would need to store the next address.

  There is still a slight possibility that the SPI peripheral  has some strange fault. I have tried disabling interrupts during the write to the SPI registers with no effect. I have also searched for glitches on the SPI bus and chip select over long time periods without finding anything.

    The key finding that indicates that the memories are responsible for the write errors is that they do not have the same number of errors. Memory D has many more than the other three. If there was an SPI problem, I would expect the write errors to be evenly distributed over all 4 memories.

4/- I am on holiday 13th to 22nd Jan

 

regards

 

Cosmo Little

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DesaiShubham
Moderator
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50 sign-ins 25 replies posted First like received

 

Hi @Cosmo_Little ,

 

>We request you please create a technical support case for further debug on the issue. Please copy me when you create case so that case is with me.

 

>Please refer the PDF Link for case creation: https://www.infineon.com/export/sites/default/en/about-infineon/company/contacts/support/images/Leaf....

 

Thanks,
Shubham

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