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Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions

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First question asked Welcome!

I've run into a problem with some FM25CL64B-GA chips in a new device.

To initialize the FRAM (not trusting the factory default values), I read a specific location (last 4 bytes) and look for a specific pattern (0xBEEFF00D), and if it isn't there I set the complete memory array to 0x00, then write my pattern to the appropriate location. On the next start, I look for the same pattern at the same address and, if the pattern is there, bypass zeroing out the array.

The problem is that I repeatably read garbage instead of my pattern at startup, and zero out the array erroneously. The chip seems to not be ready to be read. I checked the documentation and 001-84477 Rev. *J says that I need to wait a minimum of 1ms from power up to first chip select (tPU) which is what I had coded.

I'm running the chips at 3.29V (measured with a Fluke 87V), 16MHz on SCK, medium SPI pin drive current giving a good voltage swing to both rails and square edges, room temperature. To be sure that it just wasn't a bad chip, I had our tech swap the piece with another from the same lot (date code CYP 1619)

Since my micro processor has a reasonably stable clock and a 1ms tick, I delay until the top of the next tick before accessing the memory. I still have the startup problem. Okay, the processor may boot earlier than the FRAM, the tick counter may not be precise and it might tick early by a few microseconds, so I adjusted the startup delay.

So I tried increasing the startup delay to 2 and 3ms but read the wrong value, and finally at 5ms the system started reliably correctly in my tests, so I increased the startup delay to 10ms and the system starts correctly in testing. No other changes to the code or hardware. I also checked to see if the system tick (1ms tick) was correct, yes it is (within a microsecond).

Just increasing the delay before reading the FRAM fixed the issue.

Oddly, the startup time (tPU) was 10ms in the original version of the documentation, but reduced to 1ms in version *A in 2013.

So, my questions: the value of tPU is 1ms minimum, what is the recommended typical value? 5ms (which is greater than 1)? 1000ms (which is greater than 1)? Does it vary with temperature? Are there other parameters that affect my choice of delays to meet tPU?

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Hi @Andrei_C,


> Are you observing this issue only when you are reading after power-on? And if you are reading the address location without a power cycle, are you able to read the desired data?

> On how many devices are you observing this issue?

> Are you compliant with the tVR and tVF specs? Kindly share the power-up and power-down waveforms.

> Kindly share the read and write waveforms for the two cases:

  1. when tPU is 2 or 3 ms (unsuccessful read)
  2. when tPU is 10 ms (successful read)

> Please share the schematic of the FRAM part.




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