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Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions

NaMo_1534561
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Hello,

Could you provide the Soft Error Rate (SER) data of below part?

MPN  CY14B101NA-ZS25XI

Best Regards,

Naoaki Morimoto

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1 Solution
Anonymous
Not applicable

Hello Morimoto-san,

I am extremely sorry for the delay.

In static SER testing - data is written to the memory array under specified Alpha particle exposure, wait for some time (few minutes), then read and verify. This emulates the use case scenario where data written to SRAM is not frequently changing.

In non-static (or dynamic) SER testing - data is written to the memory array under Alpha particle exposed environment but for a very short wait time (varies between few ns to few us), read verify and changed again. This emulates the use case scenario where memory data frequently changes. Since stored data frequently changes in dynamic SER testing, the FIT rate for non-static (dynamic) SER is much lower than the static.

SEL or SEU is a different phenomenon where the SCR type circuit triggers and creates low resistance between VCC and GND under the effect of alpha/neurons. However, the nvSRAM triple well architecture design prevents to occur the  SEL type scenario under the specified Alpha/Neuron intensity, therefore it measure 0 FIT/Device (means no evidence of failure found).

Regards,

Nada

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6 Replies
Anonymous
Not applicable

Hello Morimoto-san

Please kindly refer to this KBA Single Event Latch-Up (SEL) and Soft Error Rate (SER) in nvSRAMs - KBA83213 on nvSRAM SER data.

Let us know if you need any clarification.

Thanks,

Nada

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NaMo_1534561
Level 5
100 replies posted 100 sign-ins 50 replies posted
Level 5

Nada-san,

Thank you for reply.

Is there actual measurement data?  Customers are requesting data to consider whether to put SER measures on the processor side.

Best Regards,

Naoaki Morimoto

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Anonymous
Not applicable

Hello Morimoto-san,

Yes we have a report on that and I already send it to you. Please check and let me know if you need any clarification.

Thanks,

Nada

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NaMo_1534561
Level 5
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Level 5

Hello Nada-san,

Thnak you for sending the report.

Could you explain different between the STATIC SER (FIT/Mbit) and the non-static SER in the Soft Error Test Results on page 2.

It shows that ALPHA STATIC SER and NEUTRON STATIC SER (FIT/Mbit) are high score, but NEUTRON SEL (FIT/Device) and THERMAL NEUTRON SER (FIT/Mbit) are almost zero.

I guess that it is caused by test conditions.

Best Regards,

Naoaki Morimoto

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NaMo_1534561
Level 5
100 replies posted 100 sign-ins 50 replies posted
Level 5

Hello,

Do you have any update?

Should I talk to customer using STATIC SER?

Best Regards,

Naoaki Morimoto

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Anonymous
Not applicable

Hello Morimoto-san,

I am extremely sorry for the delay.

In static SER testing - data is written to the memory array under specified Alpha particle exposure, wait for some time (few minutes), then read and verify. This emulates the use case scenario where data written to SRAM is not frequently changing.

In non-static (or dynamic) SER testing - data is written to the memory array under Alpha particle exposed environment but for a very short wait time (varies between few ns to few us), read verify and changed again. This emulates the use case scenario where memory data frequently changes. Since stored data frequently changes in dynamic SER testing, the FIT rate for non-static (dynamic) SER is much lower than the static.

SEL or SEU is a different phenomenon where the SCR type circuit triggers and creates low resistance between VCC and GND under the effect of alpha/neurons. However, the nvSRAM triple well architecture design prevents to occur the  SEL type scenario under the specified Alpha/Neuron intensity, therefore it measure 0 FIT/Device (means no evidence of failure found).

Regards,

Nada

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