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# FRAM write access time

We have an FM25L16B in our product. I want to know how long it takes the memory chip to write one byte to the cell of the FRAM after it has been transferred to the memory chip via SPI. I need this information to calculate the probability that a power interruption will interrupt this write cycle.

A similar question was asked in https://community.infineon.com/t5/Non-Volatile-RAM-F-RAM-NVSRAM/FRAM-access-time/td-p/119910, but the write access time was not given by @PradiptaB_11 .

Thanks,

Daniel

7 Replies
Moderator
Moderator

# Re: FRAM write access time

Hi @burgdani,

It all depends on the frequency you are operating at.
The access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus.

Thanks,

Ritiwck

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# Re: FRAM write access time

I would like to know how long the effective FM25L16B-internal write process of one byte into the FRAM cell takes. I need this information because I want to estimate how big the time window is where a power failure can lead to an invalid byte in the FRAM.

Does the effective write process also depend on the bus speed (e.g. because the data is written bit by bit into the FRAM cell or because the write-process is clocked based on the SPI speed) or does the FM25L16B first waits until one byte has been transmitted and only then writes the received byte into the FRAM cell in a write process?

Can you provide an example for calculating the effective time for writing one byte into the FRAM cell if the write process depends on the SPI bus speed?

Moderator
Moderator

# Re: FRAM write access time

Hi @burgdani,

FM25L16B first waits until one byte has been transmitted and only then writes the received byte into the FRAM cell in a write process. So, if you are operating at 1 MHz, the clock period would be 1 us, so the time taken to write a byte would be 8*(1 us) = 8 us.

Thanks,
Ritwick

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# Re: FRAM write access time

Thank you for your answer. I am not completely happy with the information.

I agree that it takes 8us to transmit one byte assuming the SCK to be 1MHz:

However, after one byte (orange) is transmitted, the SCK clock is stopped (see figure above) and therefore, according to my understanding, cannot be associated with the time it takes to write the one byte to the F-RAM array (red).

How long does it take to effectively write one byte to the F-RAM Array (copy action from Data I/O Register to F-RAM Array, red) without taking into account the time to transfer the byte (i.e. clocking into the Data I/O register, orange)?

Thanks,

Daniel

Moderator
Moderator

# Re: FRAM write access time

Hi @burgdani,

You should be compliant with the below timing diagram for correct read and write operations.

The tCSH delay will take care of the time taken to move data from buffer to memory array.

Thanks,

Ritwick

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Level 1

# Re: FRAM write access time

Thank you for your explanation.

Can you please read my summary below and confirm that this is correct.

Thanks,
Daniel

Summary

Saving 1 byte from an SPI microcontroller into the "F-RAM Array" of the FM25L16B consists of

1. transferring 1 byte via SPI into the "Data I/O Register" and
2. copying/writing the transferred byte from the "Data I/O Register" into the "F-RAM Array".

The write time to write 1 byte into the "F-RAM Array" corresponds to tCSH (Chip select hold) and takes 10ns accordingly.

If the supply voltage is removed during write access to the "F-RAM Array", there may be invalid data in the corresponding byte in the "F-RAM Array".

Moderator
Moderator

# Re: FRAM write access time

Hi @burgdani,

The total time taken to write a byte is the time covered by orange and red in the below image. And if you are writing more than 1 byte of data, the time covered by orange will increase, but red remains the same.

E.g., For 1 byte, orange is 40 us, then for 2 bytes, it would be 40 + 8 us = 48 us, and the total time would be 48 us + 10 ns = 48.01 us.

If all the 8 bits of a byte are sent, and then if there is a power-down, the data would be valid, provided you were compliant with the tVF (VDD power-down ramp rate) spec.

Thanks,
Ritwick

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