FRAM max. clk rise/fall timing

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_Frank_
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First reply posted First question asked Welcome!

Hello,

AC characteristics for SPI FRAM (FM25CL64B) is based on signal rise/fall times of 5ns, which includes CLK signal as well.

What is the max. acceptable clock rise/fall time, supported by the device?

Thanks in advance
Frank
 

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GirijaC
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50 sign-ins 25 sign-ins 10 solutions authored

Hi Frank,

We do not specify the max rise/fall time. Theoretically all values >5ns are acceptable. Condition is that signal must be monotonic. Otherwise noise will create spurious behavior near Vt, specially for slow rising signals.

Recommendation is; should not exceed 0.45*tCK. Essentially clock needs to rise to VIH within min duty cycle which is 45%. So, if operating at 1MHz, the max rise/fall time should not exceed 450ns. If its 10MHz->45ns and so on.

Thanks,

Girija

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Ritwick_S
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Hi @_Frank_,

 

The rise and fall time of an IO during output depends on the load that is connected to the FRAM pin. During testing, the IOs are tested with the datasheet load (Termination and 30pF capacitive load), but you may connect the IOs differently.

The load capacitance, trace capacitance, and the number of signals sharing the trace differ for every custom design. It is not possible to provide a rise and fall time number for all such combinations. Due to this reason, we generally recommend customers to use IBIS model simulation in combination with the controller IBIS model to get a good estimate of rise and fall time.

Now, during the Input phase, the rise and fall time of the signal depends completely on the controller IO strength. So, FRAM cannot define rise and fall time during this phase. This is the reason the datasheet does not specify the rise and fall time spec. Because it is a number that depends on board condition and not purely a function of silicon.

The IBIS model simulation will help you get more accurate results.

 

Thanks,

Ritwick

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_Frank_
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First reply posted First question asked Welcome!

Dear Ritwick,
thanks for your quick response. I fully agree with you, but my concern of max. clock slew rate is about proper edge detection.
For longer rise/fall timings, I'd assume a risk of multiple edge detection by the device, provided CLK input has no threshold hysteresis (Schmitt-trigger).

If there a max. clock slew rate limit to be kept in order to ensure error free communication?

Best regards
Frank

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_Frank_
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First reply posted First question asked Welcome!

Dear Ritwick,

could you please let me know, if there is a maximum rise/fall timing value for CLK input, which might not be exceeded by FRAM application?

Thanks in advance.
Frank

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GirijaC
Moderator
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50 sign-ins 25 sign-ins 10 solutions authored

Hi Frank,

We do not specify the max rise/fall time. Theoretically all values >5ns are acceptable. Condition is that signal must be monotonic. Otherwise noise will create spurious behavior near Vt, specially for slow rising signals.

Recommendation is; should not exceed 0.45*tCK. Essentially clock needs to rise to VIH within min duty cycle which is 45%. So, if operating at 1MHz, the max rise/fall time should not exceed 450ns. If its 10MHz->45ns and so on.

Thanks,

Girija

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