The following is the log before and after the error of "Analysis & Synthesis".
After this message, compilation failed.
Info (12128): Elaborating entity "FM28V202A" for hierarchy "FM28V202A:inst23"
Warning (10036): Verilog HDL or VHDL warning at FM28V202.v(65): object "addr_change" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at FM28V202.v(73): object "delayed_ce_" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at FM28V202.v(77): object "page_mode_ce" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at FM28V202.v(72): truncated value with size 32 to match size of target (16)
Error (10106): Verilog HDL Loop error at FM28V202.v(161): loop must terminate within 5000 iterations
Info (10648): Verilog HDL Display System Task info at FM28V202.v(165): Simulated memory array initialization with 16'hffff...
Warning (10855): Verilog HDL warning at FM28V202.v(150): initial value for variable Mem should be constant
Error (12152): Can't elaborate user hierarchy "FM28V202A:inst23"
Also, regarding the implementation of the FRAM simulation model,
"Readdata, writedata, read, write, chipselect, address" signal of "Generic Tri-State Controller" prepared by Qsys
It is also connected to the FRAM simulation model placed in the Top hierarchy via the "Tri-State Conduit Bridge" on Qsys.
The FRAM simulation model "UB, LB" is connected to GND.
However, as far as I can see the error message, it says that the description of the number of loops in the FRAM simulation model is violated.
It seemed to be a problem with the description on the FRAM simulation model side.
