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Using FM28V202AVERILOG simulation model
After compiling in the Quartus 16.1 environment, the following I got the following error message.
Error (10106): Verilog HDL Loop error at FM28V202.v(161): loop must terminate within 5000 iterations
If you know the reason, please let me know
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Hi @MAO ,
Can you attach a screen shot of the error on your system. Also can you let us know the complete list of steps you follow. Our Verilog files compiled without any errors and we were able to run the test bench code.
Thanks,
Pradipta.
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The following is the log before and after the error of "Analysis & Synthesis".
After this message, compilation failed.
Info (12128): Elaborating entity "FM28V202A" for hierarchy "FM28V202A:inst23"
Warning (10036): Verilog HDL or VHDL warning at FM28V202.v(65): object "addr_change" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at FM28V202.v(73): object "delayed_ce_" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at FM28V202.v(77): object "page_mode_ce" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at FM28V202.v(72): truncated value with size 32 to match size of target (16)
Error (10106): Verilog HDL Loop error at FM28V202.v(161): loop must terminate within 5000 iterations
Info (10648): Verilog HDL Display System Task info at FM28V202.v(165): Simulated memory array initialization with 16'hffff...
Warning (10855): Verilog HDL warning at FM28V202.v(150): initial value for variable Mem should be constant
Error (12152): Can't elaborate user hierarchy "FM28V202A:inst23"
Also, regarding the implementation of the FRAM simulation model,
"Readdata, writedata, read, write, chipselect, address" signal of "Generic Tri-State Controller" prepared by Qsys
It is also connected to the FRAM simulation model placed in the Top hierarchy via the "Tri-State Conduit Bridge" on Qsys.
The FRAM simulation model "UB, LB" is connected to GND.
However, as far as I can see the error message, it says that the description of the number of loops in the FRAM simulation model is violated.
It seemed to be a problem with the description on the FRAM simulation model side.
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I tried ① as the above solution, but I got an error.
①Comment out line 124 of config.v and set initMemFile
Can you enable it and try it? In this case Memory array
Initialization is done by reading init.dat.
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Could you give me an answer by next Wednesday?
I'm sorry I'm busy, but thank you.