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I think the FM28V202A has a capacity of 2Mbit, but even in the simulation model
Is it possible to simulate full area access for 2Mbit?
If you use a simulation model, please let us know if there are any restrictions on driver development.
(For example, access to a specific area can only be simulated, etc.)
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Hi @MAO ,
Yes the complete memory should be available to you for simulation. You should be able to simulate full access for 2 Mbit.
Also all the information related to the model is also provided in the doc file provided the Verilog model on our website. You can also refer that for further details. There should be no restrictions for driver development as per our understanding.
Thanks,
Pradipta.
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Hi @MAO ,
Yes the complete memory should be available to you for simulation. You should be able to simulate full access for 2 Mbit.
Also all the information related to the model is also provided in the doc file provided the Verilog model on our website. You can also refer that for further details. There should be no restrictions for driver development as per our understanding.
Thanks,
Pradipta.