Does FRAM operation is terminated when SPI master command is interrupted?

[NaMo_1534561]

Hello,

Does FRAM operation is terminated when SPI master command is interrupted?

For example, Suppose the SPI master asserts CS# low and the clock stops in the middle of a Read or Write command. The maximum clock stop period is about 10 seconds.

If the SPI master then resumes clock oscillation, will the FRAM continue to process this command? Or does timeout processing enter internally and the command is ignored?

CS# stays low until after the clock is stopped and re-started.

MPN: CY15B104Q-PZXI

Best Regards,

Naoaki Morimoto

[Ritwick_S]

Hi @NaMo_1534561,

Could you please clarify the statement "the clock stops in the middle of a Read or Write command"? Did you mean that clock stops after sending the read/write opcode, or is the clock stopped in between sending the opcode?

Thanks,
Ritwick

[NaMo_1534561]

Hello Ritwick-san,

Both cases are possible. The timing at which the clock stops is irregular.

Regards,

Naoaki 

[GirijaC · Accepted solution]

Hello Naoaki-san,

Yes,  F-RAM will resume the transaction once Master start the clock oscillation from previous clock stop condition during opcode cycle or address/data cycle with CS low condition.

Thanks,

Girija

[NaMo_1534561]

Hello Girija-san,

Thank you for your reply.

I understand that the F-RAM can resume the transaction from a clock interruption while CS is low.

Regards,

Naoaki