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Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions

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1.  With respect to the NVSRAM (CY14B256LA-SP25XIT) what it the structure/impedance between the power pin(s), VCC, and the storage cap Vcap.

2.  If given a step change in VCC during power on, 0 – 3.3V, what limits the current through the chip to the storage capacitor? Would that maximum current or impedance be the same for a ramped VCC, e.g. a soft-start?

3.  The data sheet would suggest that the hardware auto-recall (See Note 25. on page 13 of the datasheet) is only a function of the voltage on the VCC  and not the Vcap pin voltage, is this correct?

4.  In the CY14B256LA data sheet under maximum device ratings on page 8  there is a maximum accumulated storage time:

Maximum accumulated storage time:

At 150 C ambient temperature .......................1000 h

At 85 C ambient temperature ..................... 20 years

  • Are these limitations against the storage of data or with respect to the useful life of the component?
    1. Does the storage temperature / time impart physical changes, damage, to the component or is it just with respect to the data storage?
    2. Are there any internal manufacturing structures, e.g. flash, which are used to mask defective structures, array elements, to increase the yield of the device which would be adversely affected by the storage temperature?
  • If just with respect to the storage of data, would rewriting the array reset the 1000h accumulated storage time?
  • Can the storage temperature to data integrity, or component life, be defined? E.g. above 85C device data integrity, or life, decreases exponentially or perhaps linearly with respect to accumulated time at temperature?

5.  What are the architectural differences between the that drive the change in the auto-recall and software recall times as compared to the STK14C88? Reference Infineon app-note AN55662_Migrating_from_STK14C88-3_to_CY14B256LA-ApplicationNotes-v06_00-EN.  I’m not looking for too deep of an answer, really zoomed out or high level features would be sufficient, like the internal controller/state machine includes enhanced error detection and correction, clearing or setting of dirty data dirty bits, indicative of a un-saved write operations, slower non-volatile memory…

6.  Since the components are screened for temperature, is there an estimate for the time each component was powered during testing at elevated temperatures? I’m assuming that it was fairly minimal, a few seconds too perhaps a couple of minutes each. I guess a valid conservative estimate would be the total test time at temperature divided by the number of components tested?

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