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Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions

jupoc_3327696
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We are using CY14B116N-Z30XI nvsram in a pcmcia memory card.
The CY14B116N-Z30XI connects to a AGLP125 which generates the control signals for the nvsram and the pcmcia bus. The WE pin is pulled up by a 10k resistor and there's a 22uf cap on the VCAP pin. When the card is power cycled some cards unintentionally change data in the nvsram without any writes from the processor. The datasheet for the CY14B116N-Z30XI describes the autostore function and how to disable it using software read command sequences.  The FPGA was updated to drive HSB high by default instead of just during read/write operations, with only a weak pull-up in the nvsram otherwise. Does it make sense that driving HSB high by default would eliminate corruption in the nvsram since HSB is active low and why? If this this change doesn't fully solve the problem we could look at creating a FSM in the FPGA to create the autostore disable sequence.

 

 

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ritwicksharma
Moderator
Moderator 100 replies posted 50 solutions authored First question asked
Moderator

Hi @jupoc_3327696,

 

> Could you please confirm if you are compliant with all the datasheet specs? Like, DC Electrical, AC Switching, and AutoStore/Power-Up RECALL specs. 

ritwicksharma_0-1657104445721.png

You need to wait tHRECALL time after power cycle before any read/write operation. Also, ensure that you are meeting the VCC rise time and the power up ramp is monotonic.

 

> Could you please just perform the SRAM write, and then read the data from the SRAM and check the result (no store and recall operations) and let us know the result?

 

> Could you please share the schematic with us?

 

Thanks,

Ritwick

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ritwicksharma
Moderator
Moderator 100 replies posted 50 solutions authored First question asked
Moderator

Hi @jupoc_3327696,

 

> Could you please confirm if you are compliant with all the datasheet specs? Like, DC Electrical, AC Switching, and AutoStore/Power-Up RECALL specs. 

ritwicksharma_0-1657104445721.png

You need to wait tHRECALL time after power cycle before any read/write operation. Also, ensure that you are meeting the VCC rise time and the power up ramp is monotonic.

 

> Could you please just perform the SRAM write, and then read the data from the SRAM and check the result (no store and recall operations) and let us know the result?

 

> Could you please share the schematic with us?

 

Thanks,

Ritwick

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