About Excelon FRAM

[MAO]

Can you confirm the impact of the attached changes?

[SudheeshK]

Hello,

The document you attached tells that WP# and RESET# pins must be connected to VDD if not used, they don't have any weak internal pullup resistors. 

Impact of this change is also mentioned in the document, "There is no change to the product. Infineon recommends that customers take this opportunity to review these changes against current application notes, system design considerations and customer environment conditions to assess impact (if any) to their application."

Kindly explain your question in detail, if you are looking for any specific information.

Thanks and Regards,

Sudheesh 

[MAO]

I am sorry.
As you pointed out, the WP and REST pins hanging to Vdd have been changed to Msut.
If there is a customer who is currently using Float, I think it will be necessary to change the base or something.
I am assuming that if you use Float, the internal pull-up will be weak and it will pick up noise.
If a customer asks why the WP and REST pins need to be connected to VDD, is there a reason why this is necessary?

[Ritwick_S · Accepted solution]

Hi @MAO,

Below is a detailed explanation of your question.

Why do we need to tie the EXCELON F-RAM WPn pin to VDD if I am not using it?

The EXCELON F-RAM WPn pin is an input pin that enables the write protect feature when driven logic LOW. If the WPn remains unbiased (floating on the PCB), the input stage of the pin's pad will draw a slightly higher Vdd current when the floating input assumes a non-boolean value which can partially turn on the NMOS and PMOS of the input stage. Therefore, it is recommended to bias the WPn to VDD either using a 3-10K external pull-up resistor or directly short to VDD if not used. The additional current may not be noticeable during normal access (in active mode). However, it may be much more noticeable when the device is in low-power mode: Standby, DPD, or Hibernate.

Why do we need to tie the EXCELON Ultra F-RAM RESETn pin to VDD if I am not using it?

The EXCELON Ultra F-RAM RESETn is an input pin that keeps the device in reset when driven logic LOW. RESETn function is multiplexed with IO3, and it is enabled by setting the IO3R bit (IO3R = '1') of the config register CR2 (CR2[5]). If the RESETn is enabled and remains unbiased (floating on the PCB), the input stage of the pin's pad will draw a slightly higher VDD current when the floating input assumes a non-boolean value which can partially turn on the NMOS and PMOS of the input stage. Therefore, it is recommended to bias the RESETn to VDD either using a 3-10K external pull-up resistor or directly short to VDD, if not used.

Thanks,
Ritwick

[MAO]

Thank you for your thoughtful response.
The customer asked me why and I will answer that way.