The watchdog is one possible protection against unintentional motor activation or in case of system failure (e.g. SPI bus issues, microcontroller malfunction…), therefore it is recommended to keep it enabled. However it may be convenient to disable the WD during the development phase.
The following sequence disables the watchdog:
1. SPI Frame 1: Set the UNLOCK bit (GENCTRL1).
Important: While setting the UNLOCK bit, the WDTRIG bit must be inverted to avoid a wrong watchdog failure. The default value WDTRIG right after a power-on reset is 0.
2. SPI Frame 2: Set WDDIS (in GENCTRL2).
If a SPI frame is added between SPI Frame 1 and SPI Frame 2, then the UNLOCK bit is cleared. Consequently the WD stays enabled despite the SPI Frame 2.
This sequence requiring two consecutive SPI frames and involving two different registers, prevents a deactivation of the watchdog "by accident" with one single SPI command (e.g. due to a flipped bit). Show Less

Does the WDTRIG bit need to be inverted when changing non WD settings in GENCTRL1 register?

The WDTRIG bit must be inverted every time the GENCTRL1 register is written. Otherwise fail-safe mode is entered. This applies even if the bit settings being written do not affect the WD. I.e., if changing the current sense amplifier (CSA) gain setting CSAG1, the WDTRIG bit must still be inverted when the write occurs. Show Less

The register definition of the TLE92108/4 is optimized for 24-bit frames. However, it is possible to use 32-bit SPI frames as well. For 32-bit SPI frames, the four bytes must be sent in the following order:
1. Byte 1: Dummy byte 0x00
2. Byte 2: Address byte
3. Byte 3 and byte 4: Data word
The microcontroller receives the following information from the TLE92108-23x SDO in the following order :
1. Byte 1: Global status byte
2. Byte 2: Dummy byte 0x00
3. Byte 3 and byte 4: Response word Show Less

What is the max. possible capacitance values of CCP, CCP1, and CCP2 for the TLE9210x device family?

CCP1 is an external capacitor connected between CPC1N and CPC1P.
CCP2 is an external capacitor connected between CPC2N and CPC2P.
CCP is an external capacitor connected between VS and CP

For CCP1 and CCP2: A capacitance of 220 nF (50V rated) is recommended is is recommended not to exceed 330 nF. The internal charge pump circuit has a certain current capability, and might not be able to fully charge CCP1 and CCP2 during a charge pump cycle, if the capacitance values of CCP1 and CCP2 are too high.

For the buffer capacitor CCP between VCP and VS, 470nF is recommended. A higher value such as 1 µF is possible for lower voltage ripple at VCP. If the capacitance value is bigger, it takes longer time for the internal charge pump circuit to overcome the CP undervoltage. Show Less

What is the max. possible capacitance values of CCP, CCP1, and CCP2 for the TLE9210x device family?

CCP1 is an external capacitor connected between CPC1N and CPC1P.
CCP2 is an external capacitor connected between CPC2N and CPC2P.
CCP is an external capacitor connected between VS and CP

For CCP1 and CCP2: A capacitance of 220 nF (50V rated) is recommended is is recommended not to exceed 330 nF. The internal charge pump circuit has a certain current capability, and might not be able to fully charge CCP1 and CCP2 during a charge pump cycle, if the capacitance values of CCP1 and CCP2 are too high.

For the buffer capacitor CCP between VCP and VS, 470nF is recommended. A higher value such as 1 µF is possible for lower voltage ripple at VCP. If the capacitance value is bigger, it takes longer time for the internal charge pump circuit to overcome the CP undervoltage. Show Less

Is it okay to put 100nF at each SHx pin for the ECU level ESD protection? Are there any concerns for over-current detection / drain-source overvoltage error due to the 100 nF capacitance ?

100nF will not cause any unwanted detection failure detection
The charge duration of the 100 nF is in the range of trise and therefore well within the blank time for the drain-source overvoltage (tBLANK).
Besides, there is the additional margin with the drain-source overvoltage filter time tFVDS.
The VDS drop is expected to be below the VDS monitoring threshold, therefore, a VDS overvoltage will not be triggered.

The charge of the 100 nF cap is very fast.

Let's take an example just to have an order of magnitude: let's suppose the 100 nF is charged with let's say 5 A current. The charge duration is given by:

t = C x V / I where:
- C = 100 nF
- V is the voltage swing for the capacitor (V = VS = 13 V)
- I = 5 A
This results a charge time of t = 260 ns

260 ns is much smaller than the blank time or the VDS filter time as you stated.

Besides, such a current normally does not trigger the VDS overvoltage, because the VDS monitoring threshold is not even reached. Show Less

CCP1 is an external capacitor connected between CPC1N and CPC1P.
CCP2 is an external capacitor connected between CPC2N and CPC2P.
CCP is an external capacitor connected between VS and CP

For CCP1 and CCP2: A capacitance of 220 nF (50V rated) is recommended is is recommended not to exceed 330 nF. The internal charge pump circuit has a certain current capability, and might not be able to fully charge CCP1 and CCP2 during a charge pump cycle, if the capacitance values of CCP1 and CCP2 are too high.

For the buffer capacitor CCP between VCP and VS, 470nF is recommended. A higher value such as 1 µF is possible for lower voltage ripple at VCP. If the capacitance value is bigger, it takes longer time for the internal charge pump circuit to overcome the CP undervoltage. Show Less

The gain drift is the drift of the gain after calibration.

For example, the gain of the current sense amplifier is calibrated at 25 °C with a two point calibration (i.e. using two load currents).

The gain drift is the drift resulting from the device ageing and from the temperature drift (from Tj = -40°C to 150°C). Show Less

When are the external high-sides / low-sides turned on after a drain-source overvoltage detection?

When the status bits HSxDSOV or LSxDSOV are cleared, the half-bridge follows the content of HBxMODE.

Example 1:
1. HB1MODE = 01B: HS MOSFET is on
2. Then a VDS overvoltage is detected
- The half-bridge is turned off and the HS1DSOV status bit is set
- Note: the device keeps the content of HB1MODE unchanged to 01B, even if the HS1 is turned off
3. The DSOV status register is cleared
4. Since HB1MODE = 01B, then the external high-side MOSFET 1 is turned back on, following the content of HB1MODE

Example 2:
1. HB1MODE = 01B, HS MOSFET is on
2. Then a VDS overvoltage is detected
- The half-bridge is turned off and the HS1DSOV status bit is set
- The device keeps HB1MODE = 01B
3. The microcontroller sends a SPI frame which resets HB1MODE = 00B
4. Then the µC clears DSOV status register
5. Since HB1MODE = 00B, the external high-side and low-side MOSFETs stay off, following the content of HB1MODE, even if HS1DSOV is reset Show Less

When are the external high-sides / low-sides turned on after a drain-source overvoltage detection?

When the status bits HSxDSOV or LSxDSOV are cleared, the half-bridge follows the content of HBxMODE.

Example 1:
1. HB1MODE = 01B: HS MOSFET is on
2. Then a VDS overvoltage is detected
- The half-bridge is turned off and the HS1DSOV status bit is set
- Note: the device keeps the content of HB1MODE unchanged to 01B, even if the HS1 is turned off
3. The DSOV status register is cleared
4. Since HB1MODE = 01B, then the external high-side MOSFET 1 is turned back on, following the content of HB1MODE

Example 2:
1. HB1MODE = 01B, HS MOSFET is on
2. Then a VDS overvoltage is detected
- The half-bridge is turned off and the HS1DSOV status bit is set
- The device keeps HB1MODE = 01B
3. The microcontroller sends a SPI frame which resets HB1MODE = 00B
4. Then the µC clears DSOV status register
5. Since HB1MODE = 00B, the external high-side and low-side MOSFETs stay off, following the content of HB1MODE, even if HS1DSOV is reset Show Less