Motor Control ICs Forum Discussions

How to treat unused gate drivers when the static brake or the VS overvoltage brake are used for the TLE9210x product family?

SHx must be connected to GND if the following conditions are met:
- The half-bridge is not used
- And the corresponding external MOSFETs are not populated on the board
- And the VS overvoltage brake or the static brake are used
- And the passive drain-source overvoltage detection is activated
The SHx of the half-bridges without populated MOSFETs must be connected GND to avoid a wrong drain-source overvoltage detection.
Indeed, the device activates all low-sides MOSFETs during a VS overvoltage with bridge driver in passive mode event or when the static brake is activated.
If an unused SHx is not connected to GND, then SHx is not pulled to low because of the unpopulated MOSFET.
The floating SHx can result in VSHx – VSL > VVDSMONTHx_BRAKE and a drain-source overvoltage for the half-bridge HBx is detected. Then the device turns off all low-side MOSFETs because of the error detection.

GHx and GLx can be left open. Show Less

There is no risk in driving VDD and EN pin together from a single microcontroller I/O pin, since when EN =0 device is in Sleep mode and there is no activity taking place inside of the device. Show Less

Rotation from HS1 to LS2:
1. SPI FRAME: 0b 1100 1101 0000 0000 0000 0110
– HB1MODE = 10b HS1 ON
– HB2MODE = 01b LS2 ON
2. SPI FRAME: 0b 1100 1111 0000 0000 0000 0001
– PWM1EN = 1b PWM1 enabled
– PWM1_HB = 000b PWM mapped to HB1

Brake before the direction change:
1. SPI FRAME: 0b 1100 1101 0000 0000 0000 0100
– HB1MODE = 00b HS1 OFF
– HB2MODE = 01b LS2 ON

2. SPI FRAME: 0b 1101 1101 0000 0000 0000 0000
- PWM1EN = 0b – PWM disabled

3. SPI FRAME: 0b 1100 1101 0000 0000 0000 0101
– HB1MODE = 01b LS1 ON
– HB2MODE = 01b LS2 ON

Rotation from HS2 to LS1:
1. SPI FRAME: 0b 1100 1101 0000 0000 0000 1001
– HB1MODE = 01b LS1 ON
– HB2MODE = 10b HS2 ON

It is possible to omit the Brake step.
In this case, one has to be aware that on the direction change Back EMF voltage will be added (with the same polarity) to the supply voltage. This will result in double the inrush current we observed at switch-on of the original direction (HS1-LS2). This means that the external circuitry and MOSFETs need to be dimensioned accordingly.

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Are the charge pumps of the TLE92104 and TLE92108 still working in the case of fault condition?

In case of a fault on a half-bridge driven by the device, the charge pump of the device continues working and supplying other half-bridges that are ON.
The only conditions which deactivate the charge pump are:
- Overvoltage on the supply voltage
- Undervoltage on the supply voltage
- Under voltage on the CP pin caused by the thermal shutdown Show Less

Is it possible to independently drive HS and LS stages of a single half-bridge for the TLE9210x?

The HSx and LSx outputs of a single half-bridge cannot be independently controlled by a TLE9210x, they are always operated in a half-bridge configuration.
For a given half-bridge, e.g. HB1, if the HS gate output is on, the LS output is off, this applies in both static and PWM mode. Show Less

Here is the recommendation from Infineon.
Place the filter (both resistor and capacitor) close to the shunt resistor
• Therefore the eventual noise is filtered directly at the potential source of the disturbance (= shunt).
• This avoids that the disturbance propagates through the tracks between the shunt and CSA inputs and couples to other PCB tracks before it is filtered.
If possible: foresee a place holder for capacitors close to the device pins, but not populated. It is just in case, some noise is coupled from the noisy PCB track to the PCB tracks between the shunt resistor and the CSA inputs. Show Less

Why is the power-on reset bit of the global status byte active low at the TLE92104 and TLE92108?

Unlike the other status bits of the global status byte, the (negated) power-on reset (NPOR) bit is active low:
- NPOR = 0 after a power-on reset of the device. NPOR stays 0 until GENSTAT is cleared
- NPOR = 1 if GENSTAT is cleared
The arbitrary polarity definition of this bit allows the microcontroller to detect a shorted SDO line to GND: After a clear command on GENSTAT, NPOR should be 1(the power on-reset is “cleared”), unless SDO is shorted to GND.
If the SDO line is shorted to GND or the device is in sleep mode, then the microcontroller reads NPOR = 0, despite the attempt to clear the GENSTAT register.

Note: The microcontroller can detect a short circuit to VDD if the most significant bit (MSB) of the Global Status Register is set. Indeed, according to the SPI protocol of the TLE92108/4, the MSB of the Global Status Register must be 0, unless the SDI line is shorted to VDD. Show Less

The watchdog is one possible protection against unintentional motor activation or in case of system failure (e.g. SPI bus issues, microcontroller malfunction…), therefore it is recommended to keep it enabled. However it may be convenient to disable the WD during the development phase.
The following sequence disables the watchdog:
1. SPI Frame 1: Set the UNLOCK bit (GENCTRL1).
Important: While setting the UNLOCK bit, the WDTRIG bit must be inverted to avoid a wrong watchdog failure. The default value WDTRIG right after a power-on reset is 0.
2. SPI Frame 2: Set WDDIS (in GENCTRL2).
If a SPI frame is added between SPI Frame 1 and SPI Frame 2, then the UNLOCK bit is cleared. Consequently the WD stays enabled despite the SPI Frame 2.
This sequence requiring two consecutive SPI frames and involving two different registers, prevents a deactivation of the watchdog "by accident" with one single SPI command (e.g. due to a flipped bit). Show Less

Does the WDTRIG bit need to be inverted when changing non WD settings in GENCTRL1 register?

The WDTRIG bit must be inverted every time the GENCTRL1 register is written. Otherwise fail-safe mode is entered. This applies even if the bit settings being written do not affect the WD. I.e., if changing the current sense amplifier (CSA) gain setting CSAG1, the WDTRIG bit must still be inverted when the write occurs. Show Less

The register definition of the TLE92108/4 is optimized for 24-bit frames. However, it is possible to use 32-bit SPI frames as well. For 32-bit SPI frames, the four bytes must be sent in the following order:
1. Byte 1: Dummy byte 0x00
2. Byte 2: Address byte
3. Byte 3 and byte 4: Data word
The microcontroller receives the following information from the TLE92108-23x SDO in the following order :
1. Byte 1: Global status byte
2. Byte 2: Dummy byte 0x00
3. Byte 3 and byte 4: Response word Show Less