PDL SCB I2C Master Setup on CM0P

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cvanbeek
Level 3
Level 3
25 sign-ins 10 replies posted 10 sign-ins

Hello Infineon Support,

I'm trying to setup a I2C Master device which will run on the CM0P core of the CY8CPROTO-062-4343W proto board.  It isn't working correctly for me and I'm wondering if I setup my interrupts correctly for the CM0P core, since it's different than the setup for CM4 which is in the docs.

Here is my setup:

 

void I2C_Isr(void) {
    Cy_SCB_I2C_MasterInterrupt(mI2C_HW, &i2cContext);
}

void i2c_init(void)
{
    // Reference: https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__scb__i2c.html

    cy_en_scb_i2c_status_t initStatus;
    cy_en_sysint_status_t sysStatus;

    // Initialize I2C
    initStatus = Cy_SCB_I2C_Init(mI2C_HW, &mI2C_config, &i2cContext);
    if (initStatus != CY_SCB_I2C_SUCCESS) {
	    CY_ASSERT(0);
    }

    // Initialize the interupt
    #if (CY_CPU_CORTEX_M0P)
        const cy_stc_sysint_t i2cIntrConfig =
        {
            .intrsrc=NvicMux6_IRQn,
            .cm0psrc=mI2C_IRQ,
            .intrPriority = 3,
        };
    #else
        const cy_stc_sysint_t i2cIntrConfig =
        {
            .intrsrc=mI2C_IRQ,
            .intrPriority = 7,
        };
    #endif

    /* Hook interrupt service routine and enable interrupt */
    sysStatus = Cy_SysInt_Init(&i2cIntrConfig, &I2C_Isr);
    if (sysStatus != CY_SYSINT_SUCCESS) {
	    CY_ASSERT(0);
    }

    NVIC_EnableIRQ((IRQn_Type) i2cIntrConfig.intrSrc);

    /* Enable I2C to operate */
    Cy_SCB_I2C_Enable(mI2C_HW);

    /* Enable global interrupts */
    __enable_irq();
}

 

  What's happening is the first time I call Cy_SCB_I2C_MasterWrite(), Cy_SCB_I2C_MasterGetStatus() starts to return CY_SCB_I2C_MASTER_BUSY and never returns anything else.  It seems like this normally happens if the interrupt isn't setup correctly.  I've also confirmed that the I2C bus is not busy before the call:

 

void i2c_wait(void) {
    /* Wait for transaction completion */
    while (0UL != (CY_SCB_I2C_MASTER_BUSY & Cy_SCB_I2C_MasterGetStatus(mI2C_HW, &i2cContext))) {}
}  
    ....
    i2c_wait(); // This one returns instantly

    /* Initiate write transaction.
    *  The Start condition is generated to begin this transaction.
    */
    result = Cy_SCB_I2C_MasterWrite(mI2C_HW, &transfer, &i2cContext);

    i2c_wait(); // This one never returns

 

I've also probed the SCL and SDA lines and confirmed that the transaction never starts on the hardware.  They are always at 3.3 V, so not even the start command is sent.

Lastly, here's my configuration for the SCB block in the device configurator:

cvanbeek_0-1643144629843.png

Please let me know if there's anything I've configured wrong.

Best regards,

Cory

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1 Solution
Aashita_R
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 250 replies posted

Hi @cvanbeek ,

Please have a look at our app note here, which explains PSoC 6 MCU as dual-core system and the steps followed to create applications in each core. In this app note, please refer the section 4.1.1 which guides us through the steps for creating the CM0 + CPU application in ModusToolbox IDE. According to this, we need to make some changes in Makefile in order to get started using CM0+ core.

The CM0+ application also does not refer to the design.modus generated files by default. If you want to include these files as part of the CM0+ application, add to the COMPONENTS variable in CM0+ Makefile the following:
COMPONENTS=BSP_DESIGN_MODUS

Or if you are using a custom design.modus:
COMPONENTS=CUSTOM_DESIGN_MODUS

Please refer the above pointed resource and let us know if this helps of in case of any further query.

Best Regards,

Aashita

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3 Replies
Aashita_R
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 250 replies posted

Hi @cvanbeek ,

Please have a look at our app note here, which explains PSoC 6 MCU as dual-core system and the steps followed to create applications in each core. In this app note, please refer the section 4.1.1 which guides us through the steps for creating the CM0 + CPU application in ModusToolbox IDE. According to this, we need to make some changes in Makefile in order to get started using CM0+ core.

The CM0+ application also does not refer to the design.modus generated files by default. If you want to include these files as part of the CM0+ application, add to the COMPONENTS variable in CM0+ Makefile the following:
COMPONENTS=BSP_DESIGN_MODUS

Or if you are using a custom design.modus:
COMPONENTS=CUSTOM_DESIGN_MODUS

Please refer the above pointed resource and let us know if this helps of in case of any further query.

Best Regards,

Aashita

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Hi Aashita,

I can take a look through that app note.  I do already have COMPONENTS=CUSTOM_DESIGN_MODUS inside my Makefile.

Best regards,

Cory

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I was able to resolve this issue.  

Best regards,

Cory