Microcontrollers Forum Discussions

Hello,

We are developing the bootloader for the Infineon TC377 board.  For that, we need the preserved RAM (The memory that shouldn't be initialized with zero during the controller reset) to hold the flag. So, we tried the keywords below for No-initialization and location, but AURIX is not supporting these keywords. Instead of the below keywords, what can be used to create the memory in the RAM, so that it shouldn't be modified after reset of the microcontroller.

#pragma NOINIT(BootMode_InPreservedRAM)

#pragma LOCATION(BootMode_InPreservedRAM,0x50000000)

/*Here first we are creating the variable BootMode_InPreservedRAM as no initialization and giving the address as 0x50000000 for LOCATION*/

Thanks in advance.

I can program the psoc5 using openocd now, with some caveats. However, if an NVL entry exists, it stops.

I have a project which somehow did something to the NVL.

I understand setting the Reset condition on the Pins can cause this.  However, setting the pins to Don't Care doesn't fix this problem, so I suspect something else is causing the NVL to change.

Is there *any* gui / command line interface to find out what is causing the NVL to be set? (so it can be "fixed" in the project?)

This would not normally be a problem, but using openocd to program the psoc halts when the NVL entry is in the Creator generated hex file.  I have multiple reasons for using openocd, some of which involve production machines. Others are very fast compile/debug cycle.  (https://socmaker.com/?p=1004, and https://socmaker.com/?p=1027)

If I use objcopy, could I exclude that from the elf file for the new obj?  (before making a hex file) If so, would it be by address? If so, which address?  otherwise, how would I do that exclusion?

Is there a way to use openocd to program the NVL (perhaps kitprog in kitprog mode?) (Just checking)

Thanks!

Hi, I tried to implement the mtb-littlefs in my xmc7100D board  with few modification to mq serial-read/write program: But I am encountering an error: could you tell me why I am unable to do "

"

My COM Port:

in my lfs.c:

lfs_ssize_t lfs_file_read(lfs_t *lfs, lfs_file_t *file,
        void *buffer, lfs_size_t size) {
    int err = LFS_LOCK(lfs->cfg);
    if (err) {
        return err;
    }
    LFS_TRACE("lfs_file_read(%p, %p, %p, %"PRIu32")",
            (void*)lfs, (void*)file, buffer, size);
    printf("lfs_file_read(%p, %p, %p, %"PRIu32")",
                (void*)lfs, (void*)file, buffer, size);
    LFS_ASSERT(lfs_mlist_isopen(lfs->mlist, (struct lfs_mlist*)file));

    lfs_ssize_t res = lfs_file_rawread(lfs, file, buffer, size);

    LFS_TRACE("lfs_file_read -> %"PRId32, res);
    LFS_UNLOCK(lfs->cfg);
    return res;
}

How do I solve the LS_ASSERT function from failing?

Also how do I verify little_fs is not mounted on the internal flash but on the inbuild external flash memory.

Best,

PrasadA

你好！

在NORMAL状态下，我用WriteRow写NAR时报0xF00000AA（Writes are disabled in safety register）错误，

请问是什么原因？另外，可否提供使用WriteRow的例程？谢谢！

补充一点：这部分代码我是放在CM4里的，这可以吗？

Dear All，

               I use the DAVE ide v4  with the nano library， calling the SPI-MASTER-EnableSlaveSelectSignal() and SPI-MASTER-DisableSlaveSelectSignal() functions cannot raise or lower the CS pin of SPI. However, when sending data through SPI, when using an oscilloscope to check the status of SCL and MOSI pins, they generate waveforms that are normal, but the CS pin remains in a high level state. 

              Configure this CS pin as an IO port, manually pull up or down the CS pin, but use the BUSY flag in the TBUF register as the completion of sending. When pulling up the CS pin, there will be a situation where there is still one byte that has not been sent, but the CS pin has been pulled up.

             What may be the reason why the two API functions generated by calling cannot control the CS pin state; How can I avoid manually raising or lowering the CS pin when there is still one byte of data not sent?

Thanks.

XMC4500-E144F1024 AC #

hi

i want to use the SCR in order to reduce the power consumption , and meet some block point. please check state flow bellowing :

if SW switch to SCR domain to execute, which position will sw execute next after wake up source login and exit from SCR domain ?

Step A (step A as the SW first code after reset  )?  or back to Step B?

Dear community,
Working on a project based on CY8C4046LQI-T452 reached the stage where we need to think on the production automation and more specifically on the chip programming. For my great disappointment, there seems to be no options to do a CLI programming using the cheaper(KitProg3) option. From what I have read, reached to the following conclusion:

-Modus Toolbox CLI is not suitable as the make/build option is not desired
-PSoC Programmer does not support the target and is not going to
-mtb-programmer does not have CLI option

The last option left is using a J-Link.
Would appreciate you suggestions

Kind regards
ST