Microcontrollers Forum Discussions

The most common behaviour when a trap occurs is the controller resets and starts running the user software from the start address. 

Is it possible that when the controller encounters an error condition, the trap is generated, it undergoes a reset and does not recover from it to be run user software? 

If yes, what traps (TIN) are those?

The controller in question is Aurix 387.

Hello,

     When trying to flash the compiled project this error is thrown out:

Aurix Flasher 2.5.3.0, built on 3/17/2022 3:12:47 PM
Connected to device... [TRICORE] DAS JDS AURIX LITE KIT V1.0 (TC334)
::Loading HEX file ..........
:⚠️ The given program file is trying to write on reserved memory addresses, which will be skipped.
Overall time: 484 ms
AurixFlasher Exit Status: Fail
Flashing failed

I'm using AURIX-Studio-1.7.2 with the latest drivers.

The kicker is that I'm using the debug option, all works OK.  

Also, I'm using this project example project: https://github.com/Infineon/AURIX_code_examples/tree/master/code_examples/Blinky_LED_1_KIT_TC334_LK

Does anyone know where the problem might be?

Thanks, 

George

I am trying to run Infineon TC297TF Evaluation Board with the Infineon provided BSDL file using Trace-32. Can you please provide me the steps of commands I need to execute within Trace-32 to run the BSDL file and verify that some port input/output are working? 

Hello.

I implemented from [1] the chapter 8.14.3.1 "ECC Software Testing Support". I implemented the chapter for the DSRAM, DPRAM, and PSRAM.
[1] chapter 8.14.3.1 also states "If ECC operation is enabled (ECCCON.xEN = 1) the corrected data value (2000H) is read and an ECC error is indicated.".
Above second underlined is working for DSRAM, DPRAM, and PSRAM. That’s fine. And no question.
Above first underlined is working for DSRAM and DPRAM. That’s fine. And no question.
Above first underlined is not working for PSRAM. This is my problem.

I allow to describe my problem a little bit more detailed, with parts of my implementation. For the relevant code parts of my implementation see [2].

At [2] line 31 "POINT 1" is observed:

• errorcode has the value FCT_NO_ERROR.
• biosRamEccParityTestRegECCSTAT has the value 2.

At [2] line 38 "POINT 2" is observed:

• errorcode has the value FCT_NO_ERROR.
• biosRamEccParityTestRegECCSTAT has the value 1.

At [2] line 45 "POINT 3" is observed:

• errorcode has the value FCT_ERROR_ARGUMENT; reason: [2] line 80 "POINT 4" is executed. Note:
  • For [2] line 82 stated "xxxLocation6" were following different values observed: 0, 0xC0FA, or 4.
• biosRamEccParityTestRegECCSTAT has the value 4.

So my above stated problem boils down to my following question: Why is for the PSRAM, at [2] line 64 "POINT 5", [1] chapter 8.14.3.1 stated "If ECC operation is enabled (ECCCON.xEN = 1) the corrected data value (2000H) is read" not fulfilled?

References:
[1] https://www.infineon.com/dgdl/xe166h_um_v1.1_2009_04.pdf?fileId=db3a304328c6bd5c01291210b0cb099d
[2] Attached Ecc.pdf

Regards
Oliver.

I designed a board with a CY8CMBR3002 version with only one button used in GPO mode ( no I2C)

We made 2 batches that worked perfectly.

On the third one , capacitive key does not work.

Nothing in design has been changed since first PCB.

We exchanged the suspected 3002 with an old version and defective board works again.

The issue was reported on the initialy working board.

Same with whole  boards where we could exchage this component.

So I think something has changed in this component.

Here are the markings :

* Works : CY8CMBR3002-SX 0197468

*Fails : CY8CMBR3002-SX 035715

We are stucked for deliveries with no solution.

Any idea ?

I have built an application which test SPI  DMA,  i short the  pins MOSI and MISO,   and  uses two DMA channels (  DataWire 0, Channels 20 and 21).    RX trigger  channels20,TX trigger channels 21.  

  it compiles and runs correctly on the CM4 processor. I'm now trying to move that functionality to the CM0+ processor,

 I do   COMPONENTS=BSP_DESIGN_MODUS inside my Makefile,and  setup  interrupts  for the CM0P core.

 it won't work.

when spi sending is finished,program enters DMA transmission interrupt,

the function  Cy_DMA_Channel_GetInterruptStatusMasked always return 0.

Please see the attached project.

I am attaching project .Thank you so much.. 

Thank you so much. 

Recently, I studied the Sflash  write operation of CYT4BF, and found that the parameter description in TRM seems to be inconsistent with the reality.

The description in TRM is attached.

According to its description,  I only need to set opcode, blocking mode, flash address and data address four parameters. The fact is, data is always written from sflash.untoc2_object_size, and data will be written to SFLASH from data address until hardFault is generated.

A description of the data length seems to be missing from the description of the parameter......

I can't get an Interrupt to work with the XMC4800 Controller.

The rising edge of Pin 0.9 is supposed to trigger the interrupt, please tell me where i am mistaking:

    //Setting p0.9 as Input
XMC_GPIO_SetMode(XMC_GPIO_PORT0, 9,XMC_GPIO_MODE_INPUT_PULL_DOWN);

//ERU Config
XMC_ERU_ETL_CONFIG_t eruInit;
eruInit.input_b = ERU0_ETL1_INPUTB_P0_9;
eruInit.edge_detection = XMC_ERU_ETL_EDGE_DETECTION_RISING;
eruInit.enable_output_trigger = true;
eruInit.output_trigger_channel = XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0;



//OGU Config
XMC_ERU_OGU_CONFIG_t oguInit;
oguInit.service_request = XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER;

//ERU and OGU Init:
XMC_ERU_ETL_Init(ERU0_ETL1, &eruInit);
XMC_ERU_OGU_Init(ERU0_OGU0, &oguInit);

//enable Interrupt
NVIC_SetPriority(ERU0_0_IRQn,3);
NVIC_EnableIRQ(ERU0_0_IRQn);



and then my IRQ Handler:

void ERU0_0_IRQHandler(void)
{

    //set breakpoint and be happy when the code arrives here

}

Do I use the right ERU, ETL, OGU? Is everything configured properly? I read something that I have to call a Method "ClearEventStatus" in xmc4800, but I don't know what could be a valid argument.

Dears. 

Is there any function inside of MCU which takes the port short test between 2 gpio ?

If yes, Could I get some sample code ? 

If not, would you give us your idea about how to implement port short test using suitable CYT2B95 features ? 

Thanks and best regards, 

Kevin Han.  

Hi All,

What is the local RAM size of HSM for TC237?

it seems that the local RAM size is different with TC275.

Regards,

WS