Memories Forum Discussions
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Nor Flash
The NOR Flash Memory forum discusses critical safety features for automotive and industrial systems, and Semper NOR Flash Memory with ASIL-B compliant and ASIL-D-ready.
Hyper Flash
The HyperFlash NOR Flash memories Forum offers discussions on automotive advanced driver assistance systems (ADAS), automotive instrument cluster, automotive infotainment systems, and communication equipment.
Hyper RAM
HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.
Non Volatile RAM (F-RAM & NVSRAM)
Non-volatile RAM forum discusses Technology such as F-RAM and nvSRAM, which combine non-volatile data storage up to 16Mbit density with the high performance of RAM. These low-power memories offer high endurance, high data retention and instant non-volatility without external battery back-up, enabling system reliability and cost reduction.
Featured Discussions
The S29AL008J70BFI010 datasheet lists the sector trace time as "10s",
The S29AL008J70BFI010 datasheet lists a maximum sector trace time of 10s.
I understand from the above description that if it takes more than 10 seconds to execute a sector trace, it is considered to be abnormal, Is this correct?
Hi!
I am using the multichip S76HL512TC0BHB000 (HyperRam + HyperFlash) which is based on the HyperFlash S26HL512T.
Using a STM32 MCU and the HAL-API, I am struggling a lot in order to reading flash-ID or StatusReg. I am basically just reading "0xFF:s" whatever I try..
Is there any example available?
Show LessThere is no mention of 3V for Rev. R in the English version of this datasheet.
The CY62167GE30-45ZXIT datasheet has a description.
Is it some kind of mistake? Please let me know if there is a reason.
Show Less
Hello,
Do you know if there is SEE testing data available for the CY7C185 SRAM?
-Chris
Hello friend
I am using S25FL256L QSPI flash on an Intel Tornado VE FPGA and have scripted for flash programming via JTAG mode in Quartus Programmer. For read ID autodetected as QSPI 256MB flash, the blank check process completed successfully, but failed at the program stage.
Programming fails at about 33% and programming completes. The following error is displayed:
Error (20064): Error status: Status 2 register read returned 0xFF. Does not match the expected data (0x00). Error (19117): Programming failed on flash 1 at address 0X00BB0100. Error (209012): The operation failed."
When reading the status 1 (0x05) and status 2 registers (0x07), the value of address 0x00BB0100 is returned as 0XFF. To write a page in 4-byte addressing mode, use the 0x12 command. For addresses before 0x00BB0100, the error does not occur because the read status 1 register (0x05) and the status 2 register (0x07) were added.
Can you tell me the cause of this error CAN CAN .
Thank you
Sneharu B.
Show LessHi Team,
I am working on CY62157EV30LL 45ZXi SRAM chip on imx53 processor connected through EIM interface.
1.When I write data , it hsows as written proper data but when reading it shows same 2 byte data reading for other 2 bytes also.
Example, 0x12345678 is written , when read backs it shows as 0x12341234
2. When I read for next address and so on , it shows the previously read value only like 0x12341234 as shown below
debian@arm:~$ sudo ./devmem2 0xf0000000 w 0x12345678
/dev/mem opened.
Memory mapped at address 0xb6fed000.
Value at address 0xF0000000 (0xb6fed000): 0xABCDABCD
Written 0x12345678; readback 0x12341234
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$ sudo ./devmem2 0xf0000000
/dev/mem opened.
Memory mapped at address 0xb6ff0000.
Value at address 0xF0000000 (0xb6ff0000): 0x12341234
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$ sudo ./devmem2 0xf0000004
/dev/mem opened.
Memory mapped at address 0xb6fde000.
Value at address 0xF0000004 (0xb6fde004): 0x12341234
debian@arm:~$ sudo ./devmem2 0xf0000008
/dev/mem opened.
Memory mapped at address 0xb6fbe000.
Value at address 0xF0000008 (0xb6fbe008): 0x12341234
3.Can anyine tell me what are the working timing parameters to be configured on imx side for cy6215 sram chip.
4.How to change the EIM frequency
Show LessWould you be able to provide the floor life of the parts or the amount of
time we have to do the inspection before a bake out is required for P/N S25FS128SAGMFI100
I referenced J-STD-033 and the floor life for level 3 moisture sensitive
part is 168 hours. Is that the case with these parts?
Thank you.
Show LessHello,
The customer is considering reducing the power consumption of equipment that is in standby mode for a long period of time.
The power supply to Sync SRAM cannot be stopped because it is shared with other devices.
Therefore, I'm thinking of stopping the clock signal from FPGA to SRAM to reduce power consumption.
1) What is the current consumption of SRAM in Standby: Clock stopped?
2) This SRAM has DOFF# (PLL turn off).
Is it possible to reduce power consumption by setting this pin to High as well?
What is the current consumption with Clock stopped and PLL turned off?
MPN: CY7C2265KV18-550BZXI
Best regards,
Naoaki Morimoto
Show LessPlease help to check the chip, may i know the whether the chip construction is correct
CY62157EV30LL-45ZSXIT DC 2237 Lot# 612226025 COO: Philippines
Show Less
Part Number:CY62187EV30LL-55BAXI
Date Code::2243; 2231、2225
Problem description:The part number is CY62187EV30LL-55BAXI. Part Dies with date codes 2231 and 2225 are shown in pictures 1, 2 and 3. The part die with date code 2243 is shown in pictures 4, 5 and 6.
Are both kinds of die applicable to this part?
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