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The NOR Flash Memory forum discusses critical safety features for automotive and industrial systems, and Semper NOR Flash Memory with ASIL-B compliant and ASIL-D-ready.
The HyperFlash NOR Flash memories Forum offers discussions on automotive advanced driver assistance systems (ADAS), automotive instrument cluster, automotive infotainment systems, and communication equipment.
HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.
Non-volatile RAM forum discusses Technology such as F-RAM and nvSRAM, which combine non-volatile data storage up to 16Mbit density with the high performance of RAM. These low-power memories offer high endurance, high data retention and instant non-volatility without external battery back-up, enabling system reliability and cost reduction.
Discussion forum for Specialty Memory topics.
Discussion forum for SRAM related topics.
Tried to apply driver patches provided at Memory Software for Serial NOR - Infineon Technologies on Linux kernel 5.10, but it fails. Is there generic upstream driver support for this flash device?Show Less
Does anyone have radiation test data on FRAM CY15B102Q (e.g. full part number CY15B102Q-SXM or similar) or on this part family? Looking for gamma “total irradiation dose (TID)” or “single event effects (SEE)”/heavy ion test results.Show Less
1. With respect to the NVSRAM (CY14B256LA-SP25XIT) what it the structure/impedance between the power pin(s), VCC, and the storage cap Vcap.
2. If given a step change in VCC during power on, 0 – 3.3V, what limits the current through the chip to the storage capacitor? Would that maximum current or impedance be the same for a ramped VCC, e.g. a soft-start?
3. The data sheet would suggest that the hardware auto-recall (See Note 25. on page 13 of the datasheet) is only a function of the voltage on the VCC and not the Vcap pin voltage, is this correct?
4. In the CY14B256LA data sheet under maximum device ratings on page 8 there is a maximum accumulated storage time:
Maximum accumulated storage time:
At 150 C ambient temperature .......................1000 h
At 85 C ambient temperature ..................... 20 years
- Are these limitations against the storage of data or with respect to the useful life of the component?
- Does the storage temperature / time impart physical changes, damage, to the component or is it just with respect to the data storage?
- Are there any internal manufacturing structures, e.g. flash, which are used to mask defective structures, array elements, to increase the yield of the device which would be adversely affected by the storage temperature?
5. What are the architectural differences between the that drive the change in the auto-recall and software recall times as compared to the STK14C88? Reference Infineon app-note AN55662_Migrating_from_STK14C88-3_to_CY14B256LA-ApplicationNotes-v06_00-EN. I’m not looking for too deep of an answer, really zoomed out or high level features would be sufficient, like the internal controller/state machine includes enhanced error detection and correction, clearing or setting of dirty data dirty bits, indicative of a un-saved write operations, slower non-volatile memory…
6. Since the components are screened for temperature, is there an estimate for the time each component was powered during testing at elevated temperatures? I’m assuming that it was fairly minimal, a few seconds too perhaps a couple of minutes each. I guess a valid conservative estimate would be the total test time at temperature divided by the number of components tested?Show Less
Soft Error Rate discussion on NvRAM in thread from 10/16/2018 06:00PM provided a Report file to the discussion initiator. Are similar SEU/SEL report files available on NvRAM parts STK14C88-3NF35I and CY14B256LA-SZ25XIT?
We are using the CY7C4122KV13/CY7C4142KV13 SRAM in our design, with the address parity logic enabled. For the same:
1) We need the switching characteristics and Switching Waveforms for Address Parity and Parity Error operations as they were not available in the product datasheet.
2) Also, I have a two part query I'll illustrated with an example. Suppose we initiated a transaction T0 and within the RL cycles of T0, we initiate two more transactions T1 and T2. After RL cycles, we receive a Parity Error for T0. Then:
a) if the parity error counter indicates there was only 1 error and after clearing the parity error, should all the transactions. i.e. T0, T1 and T2 need to be repeated or only the first transaction (T0).
b) related to this, if the parity error counter indicates there were 2 errors, does this imply that the first 2 consecutive transactions (T0 and T1) failed or can it be T0 and T2?
It would be ideal if a dedicated documentation for the address parity implementation is available.
I currently specify using the commercial/automotive version of this part (AC10), and am trying to evaluate if the military version (EC10) can be used instead.
The datasheet for the commercial/automotive version shows Cycling Endurance of 100,000 Program-Erase Cycles (min), and the military version shows a Cycling Endurance of only 100 Program-Erase Cycles (min).
If I were to use the military version in the commercial temp range (-40 to +85 C), would the endurance of the military part approach the commercial, or is this lower value typical of the military part?
Are there any other differences between the versions that would make the military version not okay to use?
I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing specification all together.
Here is the link to the question: (Please review it, I'm not pasting it here to not to duplicate)
For the CLK, DQ and RWDS timings, it seems like the datasheet values are valid only up to ~65 MHz, although it is specified up to 133 MHz. Delay values and the valid areas of given signals doesn't add up and there seems to be a mismatch.
Has anyone ever tried to design the interface themselves or debugged the interface above ~65 MHz (CLK)? I'd like to see the DQs and RWDS signals (measured) above these clock frequencies.
Thank you.Show Less