Memories Forum Discussions

Is there any command or method to batch erase regarding the non-volatile part of NvSRAM?
Although it is OK to perform clear (WRITE) processing from the upper CPU to all addresses,
However, with an access time of 45ns, it would take several tens of ms to clear all 16Mbit addresses, so I was wondering if there is a process that can clear all addresses in one shot.
We would appreciate your confirmation.

Hi!

I am using the multichip S76HL512TC0BHB000 (HyperRam + HyperFlash) which is based on the HyperFlash S26HL512T.

Using a STM32 MCU and the HAL-API, I am struggling a lot in order to reading flash-ID or StatusReg. I am basically just reading "0xFF:s" whatever I try..

Is there any example available?

Hello,

I am looking for S70KL1283 IBIS models for simulations, but I cannot find it.

The model I need is S70KL1283DPBHV020 

Thank you.

I am trying to change the "Infineon Endurance Flex architecture Selection Register" of S25HL512. for example, After doing WRENB_0_0(0x06), 0x71,0x00,0x00,0x50,0xFD in WRARG_C_1 "Infineon Endurance Flex architecture Selection" There is no change in "Register". Do I need any other commands?

Also
https://www.mouser.com/datasheet/2/196/Infineon_6_10_22_S25HS256T_S25HS512T_S25HS01GT_S25-3003708.pdf
to P33 of

15. It is required that the high endurance data and long data retention
regions are configured at the time the device is first powered-up by the
customer.
Once configured, they can never be changed again

There is a description. This doesn't mean the one time you turn on the device after leaving the factory, right?
This means that it can only be done once after the device is powered on, so if you haven't rewritten it, you can understand that it can be done at any time, right?

Hi,

I am using  SPI Serial Flash Memory, 512Mbit, SO16 package in one of my design. I am finding many chips getting faulty in 5 to 6 months of operation in field as all access fail post that.

On analyzing one of the field return card. I am able to read device ID of this part but starting few sectors read/ write is not consistent and finding number of places data read not matching with data written.

We tried to reprogram multiple times but data integrity is not there in various sectors belong to first bank.

Device ID is getting detected by firmware always. Just printing one uboot print of processor log.

Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 64 MiB

Since data is not consistent in various sectors and we are using this as processor boot memory, so processor gets stuck during bootup.

We are using  mostly first bank (16MB) location only for processor uboot. On faulty chip, we found read/write access to locations 4MB onwards (all 3 banks except first) is ok. Since it is processor boot memory, so would be read just once during processor boot and write only if any image upgrade needed which is rare.

Datasheet mentions 100,000 Program-Erase Cycles on any sector typical. These sites are not having power backup and almost gets power cycle on daily basis but it does not explain endurance of sectors.

We noticed that part S25FL512SAGMFIR11 used is with VIO option but this pin is kept NC in our design. Measured voltage at this pin is 3.3V but dips to 2.5V while doing any access in working chips too. Below is the measurement done in one of the working board. 

Host is operating at 3.3V  IO level which is the same supply of flash VCC.

Thanks

Anurag