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The NOR Flash Memory forum discusses critical safety features for automotive and industrial systems, and Semper NOR Flash Memory with ASIL-B compliant and ASIL-D-ready.
The HyperFlash NOR Flash memories Forum offers discussions on automotive advanced driver assistance systems (ADAS), automotive instrument cluster, automotive infotainment systems, and communication equipment.
HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.
Non-volatile RAM forum discusses Technology such as F-RAM and nvSRAM, which combine non-volatile data storage up to 16Mbit density with the high performance of RAM. These low-power memories offer high endurance, high data retention and instant non-volatility without external battery back-up, enabling system reliability and cost reduction.
Discussion forum for Specialty Memory topics.
Discussion forum for SRAM related topics.
It is a matter of S29GL512S11TFIV10.
VCC = 3.3V
VIO = 1.8V
I plan to use it in, but according to the data sheet, the input order is
It seems that the startup is started in the order of VCC → VIO, and the startup is lowered due to the relationship of VCC ← VIO.
I have a question, but I have the following two points.
1. 1. In terms of design, I think there is no problem with the rise of VCC → VIO.
VIO (all terminal voltages follow the potential of this VIO) rises about 10 msec after booting VCC.
Is there any problem with such a sequence?
2. 2. In terms of design, I think that there is no problem with the fall of VCC ← VIO.
After starting VIO (all terminal voltages follow the potential of this VIO), about 5 msec
After that, VCC will drop.
Is there any problem with such a sequence?
DSP is testing to write up to 1MB of data with S25FL128L memory through SPI communication.
I wrote 16byte data in memory and checked R/W up to 1 block (64KB) (SPI Baudrate : 30Mhz)
The problem occurs when 1 block (End Address: 0x0ff) is written and the next 2 Blocks (Start Address: 0x1000) is written.
1. Data is not written normally in 2 Blocks.
2. Writing data in 2 Blocks changes the data in 1 Block.
please share your knowledge
We've been using your CY14E256LA-SZ45XI in our PCB designs for many years now and it's been a great and reliable part for us. Unfortunately, we've gotten the same bad news that others in this forum have posted about in that the part is going obsolete and there are last time buys being accepted up until Dec of 2022.
We presently use it with a 5V 8051 microcontroller.
Do you have any recommendations for a replacement part, even if it's not pin compatible?
We see many parts out there, but most are 3.3V compliant.
We thought that your "FM1808B-SG" FRAM would effectively be a drop in replacement (with a minor board layout change). However, a further inspection of its data sheet indicates that each memory access must have a separate strobe of the chip enable line.
Looking at an analyzer capture of our present design, our 8051 will keep the chip enable low (top row signal) for consecutive writes to different memory locations:
Based on this plot and your FRAM data sheet, I assume I'm reading it correctly at that the "FM1808B-SG" would not be compliant with our 8051 memory control timing?Show Less
For Flash S29GL064S90TFI030, during Parallel NOR Flash Sector Erase operation how to read other sectors data? Is it possible to do so? I am planning to use Status Register to check the status of the Erase operation.
Do I need to initiate Read Array command during status check loop to read the Flash memory data for other sector? Will it allow doing this?Show Less
I am Anil Patil. I am working on the Flash driver for S29GL032N on ADSP BF534.
We are facing one issue with the Flash driver. The firmware application does not use any RTOS or OS.
When Flash driver is in Erase operation and status is being checked for completion, if we try to access contents of some other sectors in the Flash, it reads the status of the ongoing Erase operation. Expectation is other sectors memory locations should be able read the programmed data. Instead it reads the status of the Erase operation.
Is this the right behavior of the Flash. Datasheet mentions that the status will be available if the access address is for the sector being erased. But this is not correct, other sectors also reads the same ongoing operation status instead of the programmed content in that Flash memory area.
Could you help us solve this issue. We need to access the rest of the sectors data while operations like Erase or Write are in progress. Flash programmed data read accesses for other Sectors should not be blocked during these operations. Can this be done? If yes, how?
I am sharing you the schematic sections of the PCB we are using interfacing the Flash to the BF534 DSP for your easy reference.
Also, below is the debug data which will help you to understand the issue.
Normally when there is no Erase or Program operation going on below is the Flash content for some other sector where we have our data.
But while Erase operation is in progress we see different data in those sectors shown below. This data is clearly the Status of the ongoing Flash operation and not what is actually programmed in Flash in those locations.
Hope you understand the issue what is happening.
Let us know if you understood the issue or need help understand some of the above part.
Let us know if there is any solution for the above problem we are facing.
M: +91 9049810593Show Less
Tried to apply driver patches provided at Memory Software for Serial NOR - Infineon Technologies on Linux kernel 5.10, but it fails. Is there generic upstream driver support for this flash device?Show Less
In the CY7C1380KV33 data sheet which Electrical and Switching parameters are tested at temperature and which are only tested at lab ambient? Are all components subjected to temperature testing or are only a sample per lot, date code... tested at temperature?Show Less
To Technical Support:
I was wondering if you could provide die verification for one of your products, S25FL128SAGNFI011. Upon exposing the die, the markings revealed 98740A. My question is are these markings correct for this device?
Our company does component authentication for a government prime contractor who requires to have the die markings match the external markings exactly or receive verification from the manufacturer.
I have included pictures of the component going through authentication testing and a picture of the die markings revealed post decapsulation.
Thank you in advance for any assistance that you are able to provide.
Kind RegardsShow Less
I want to use S26KL128SDABHN030 memory with STM32L4+ microcontroller. I read that this memory has DCARS feature. Is it possible to disable it to use this memory without PSC signal?Show Less