Memories Forum Discussions
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Nor Flash
The NOR Flash Memory forum discusses critical safety features for automotive and industrial systems, and Semper NOR Flash Memory with ASIL-B compliant and ASIL-D-ready.
Hyper Flash
The HyperFlash NOR Flash memories Forum offers discussions on automotive advanced driver assistance systems (ADAS), automotive instrument cluster, automotive infotainment systems, and communication equipment.
Hyper RAM
HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.
Non Volatile RAM (F-RAM & NVSRAM)
Non-volatile RAM forum discusses Technology such as F-RAM and nvSRAM, which combine non-volatile data storage up to 16Mbit density with the high performance of RAM. These low-power memories offer high endurance, high data retention and instant non-volatility without external battery back-up, enabling system reliability and cost reduction.
Featured Discussions
Hi,
I am having difficulty sending software controlled autostore disable. I think I am interpreting the datasheet reads incorrectly. Is there a more detailed document regarding the software commands?
The data sheet states that sequential reads of 0x4e38, 0xb1c7, 0x83e0, 0x7c1f, 0x703f, 0x8b45. The CY14B108N has 19 address pins while there are only 16 pins defined with these hex address.
I have assumed that A18,A17,A16 are set to zero and not used.
A15 - A0 <-address bits used
0100 1110 0011 1000 <- binary first read
4 E 3 8 <- First read
Thus,
(A15 = 0, A14=1, A13=0, A12=0) = 4xh
(A11=1, A10=1, A9=1, A8=0) = Exh
etc.....
This should be straight forward, but I notce there is small print in datasheet under truth table that states.....
6. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A14–A2) are used to control software modes.
Rest of the address lines are don’t care.
Again, there are 16 bits defined in the hex value but now with this statement only 12 bits matter?
Can someone please explain this?
I have attached waveform of the 6 reads, does this look correct?
Thanks,
Rad
Show LessHi,
Anyone have any ideas of what I should check, regarding why my first address always contains 0000h upon power-up restore, even though the rest of the locations appear to contain what was stored using autostore. All of my SRAM writes and reads are correct it is only upon restore that the first address read is incorrect and all zeros.
Thanks,
Rad
Show LessHi,
We have a product using a 70ns SRAM low power version and recently has swithed to a 45nS second source(lower power consumtion then the orginal one). and the product started to have some strange failure, had spend some time checking on various parts and found the replacing the SRAM with the slower one fix the problem. We are using a 8051 type controller. What would be the problem, we looked at the bus signal and all seems to be clean.
Show Less Cypress packs 64Mbit memory in SRAM chips that are sized 8.0 mm x 9.5 mm. To get a comparable estimate of the size, the 1 dollar coin has a diameter of 26.5mm. That is, the dollar coin covers an area equivalent to 7 such chips. Talk about value for money!
These chips are designed to operate at a cycle time of 12ns. What is the timescale equivalent to? Well, the human heart pumps blood 72 times every minute. In that one minute, the Cypress chip can support 5 billion read / write operations! One can only marvel at such technological prowess.
The chips have been built in 90nm CMOS technology. That is, a single transistor could be as tiny as 90 nm in length. What is the dimensional equivalent? The human hair is roughly that thick, irrespective of the shampoo / conditioner that we use!. Imagine a switch (or a transistor!) that could be only as wide as a single hair strand!
These chips are guaranteed for high performance and cater to niche markets including storage servers, switches and routers, testing equipment, high-end security systems and military systems
And in what packages do these "dynamites" come in? They are available in RoHS-compliant 48-BGA packages with the smallest footprint.
The I/O configurations supported are both 16-bit and 8-bit, with a power supply of 3V.
A high resolution pic @ http://www.cypress.com/go/pr/3264asyncphoto
The press release covering the launch @ http://www.cypress.com/?rID=43301
The datasheets @ http://www.cypress.com/?rID=49137
Here's an in-depth article from a Cypress author on the basics of OBFL: http://www.industrialcontroldesignline.com/howto/224900386. Enjoy!
Show LessHello!
I am looking for a low cost way to connect a Cypress parallel NVSRAM to the Intel LPC bus, does anyone have a reference design approach or recommendations as to how to accomplish this? We considered using a CPLD, but we would have to develop this and we're looking for a faster, simplier way if possible. Any suggestions would be appreciated.
Thanks in advance -
Mike
Show LessHi.
Some of Delta39K Family has Self-boot in one chip.
Is it possible to access data on flash memory from the implemented system. Is there any possibility to use data stored in flash memory implemented by the unit? I want use some part of integrated self-boot memory as "read only" memory.
How hard it can be?
Sorry for My English.
Reagards.
I have a table stored in part of the STK14CA8-N25I nvSRAM. This table is stored first time at the production line at the begining of the product life. The table is NOT supposed to be updated during the unit life cycle. Every power-up the table is being read from the memory and used by the product functionality.
Unfortunately, in several units the table was disrupted and few bits, in random places, changes their value from '0' to '1'. (The memory nas NOT erased or "run over", just disrupted in some random bits).
It sounds very similar to the Single Enent Upset (SEU) described in AN15979 but it occurs too much frequent.
Have you meet this phenomena before in nvSRAM devices ? do you have recomandations how to solve this memory disruption ?
Show LessDear Sir,
I am using the CY14B101P for one of application for data logging. Following design support from you:
1. Operating voltage: I am planning to provide 3.3V regulated voltage to the NVSRAM.
Is it okay or any suggestions?
2. Controller Interface: My uC operates with 5V. 5V-3.3V & 3.3V-5V converter using transistor (BC848) were used in between the uC & NVSRAM.
Is it okay or any suggestions?
3. 3.6V battery Ni-Cd battery, I am planning to provide to NVSRAM, after suitable voltage drop (3.2V), using 2 diodes in series.
Is it okay or any suggestions?
4. I am planning to charge the Ni-Cd battery using 5V supply with a suitable diode & resistor combination. Shall I charge the battery, when connected to NVSRAM, with the presence of 3.3v supply to NVSRAM?
Kindly send your reply.
With regards,
Jayaraj.A
Show Less