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Memories Forum Discussions

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Nor Flash

The NOR Flash Memory forum discusses critical safety features for automotive and industrial systems, and Semper NOR Flash Memory with ASIL-B compliant and ASIL-D-ready.

9046633 1697

Hyper Flash

The HyperFlash NOR Flash memories Forum offers discussions on automotive advanced driver assistance systems (ADAS), automotive instrument cluster, automotive infotainment systems, and communication equipment.

545071 109

Hyper RAM

HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.

491669 107

Non Volatile RAM (F-RAM & NVSRAM)

Non-volatile RAM forum discusses Technology such as F-RAM and nvSRAM, which combine non-volatile data storage up to 16Mbit density with the high performance of RAM. These low-power memories offer high endurance, high data retention and instant non-volatility without external battery back-up, enabling system reliability and cost reduction.

1458238 501

SRAM

Discussion forum for SRAM related topics.

1256370 468
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Anonymous
Specialty Memory
Chip Disable Issue Fixed
solved msg Solved
        Cypress had the following issue with the CY7C131E/131AE/136E/136AE Dual Port Static RAM:Chip Enable pin (CE) does not tristate I/Os of the Dua... Show More
By Anonymous
calender Sep 15, 2013
views
735
Replies
1
Anonymous
Non Volatile RAM (F-RAM & NVSRAM)
FRAM Radiation test data
solved msg Solved
Hi,    Do you have any test data available for radiation exposure and SEU/SEL on the FRAM parts? I'm specifically looking at FM22LD16 parts, but anyth... Show More
By Anonymous
calender Sep 2, 2013
views
1029
Replies
2
Anonymous
SRAM
What is the type of jitter specified by tKC Var (Clock Phase Jitter) in ...
solved msg Solved
By Anonymous
calender Sep 15, 2013
views
266
Replies
1
Anonymous
SRAM
Success
solved msg Solved
 Hi         I thank to Pritesh for helping me. Finally the problem in the termination and enabling. It is sloved .Thanking to all who replied for my p... Show More
By Anonymous
calender Aug 22, 2013
views
377
Replies
1
Anonymous
SRAM
How the Resistance are connected
        Hi Can i have picture of the resistance are connected between the memory and FPGA(memory controller). I have see the knowledge article of the ... Show More
By Anonymous
calender Aug 6, 2013
views
1010
Replies
4
Anonymous
SRAM
QDRll+ memory Termination
 Hi         In the qdrll+ memory controller ,     Case 1: The ODT is enabled (LOW) RQ=182ohms then input impedance = 182/3.33 is 54.65ohms and  output... Show More
By Anonymous
calender Aug 12, 2013
views
364
Replies
1
Anonymous
SRAM
IO-standard and resistance QDRll+
solved msg Solved
Hi       I want to know the connection  of the resistance between the memory and FPGA. how the resistance are placed and connected to each other.    T... Show More
By Anonymous
calender Aug 5, 2013
views
505
Replies
2
Anonymous
SRAM
IO-standard
solved msg Solved
        Hi The IOstandards of the memory of the qdrll+.    Show More
By Anonymous
calender Aug 2, 2013
views
1433
Replies
7
Anonymous
SRAM
IO-standard of the QDRll+ memory sram
solved msg Solved
        Hi The IOstandards of the memory of the qdrll+.    Show More
By Anonymous
calender Aug 2, 2013
views
417
Replies
1
Anonymous
SRAM
qdrll+ memory controlle rwith sram
solved msg Solved
 Hi,                   I want to know the number of the cycles till CQ/CQ# is stable.In the xilinx IP-Core it is given that 2048 cycles for the clock ... Show More
By Anonymous
calender Jul 31, 2013
views
505
Replies
3
Category Information

Memories

Memory Discussion Forums discussions regarding NOR Flash, SRAM, nvSRAM and F-RAM - performance and reliability with discrete memory densities ranging from 4K-bit to 2G-bit topics.