Memories Forum Discussions

Hi everyone,

I'm a last year student with a question about an issue with CY62148EV30LL-55SXI. On my test card, I can write without problem, but the read operation induces much noise in the circuit.

 
First I thought it was a problem with the circuit, so I checked without the memory and circuit works fine, no shorts or wire issues. I'm also following official Cypress guidelines on bypass capacitors.

Since I'm working on stripboard with adapters, I thought it would be a track length/impedence issue, but since the write and read operation works similarly, I don't really know what's going on.

My only guess left is that the memory has trouble driving the data line for reading operation (?), whereas the microcontroller has no trouble driving the data line for writing operation.

What surprises me is that I don't really write/read fast (Instruction clock is at 4MHz => Write at 3,33 kHz, that would be rather slow), the noise induces some errors but with a software verification system, I managed to eliminate most of them. I eliminated all (I need to see with extended test to be sure) errors with lowering alimentation from 3.3V to 3V.

Speed is not my objective, but this issue (even if I found almost-shamanic workarounds) is still puzzling me and I would like, if possible, advice from a much more experienced person, that would be very nice.

Another question that may be dumb, but I want to be sure: If I want to use several memories sharing data line and address line, can I keep the others memories in Chip Select enabled, Output/Write disabled while the other one is operating? (I think that yes, but I want confirmation)

Sorry for the long post, I hope that it makes sense (since English is not my main language)

Thanks in advance

Axel

Hello,

I appear to have several CY14B108N that are repeatedly performing partial autostores to the lower addresses during powerdown even though the autostore has been software disabled. I have others that repeatedly work properly so I am confident that I am disabling correctly. I am also fairly confident that I am not accidentally triggereing the HSB pin to perform a hardware store. What else is there to check? My thought is that these devices have something wrong with their disable autostore circuitry, but how likely is this? Is this feature electrically tested before delivery? What else should I check that could interfere with the disable autostore and allow a partial autostore to the lower addresses to take place during powerdown? Also, since my lower addresses appear to be affected, how does the store occur across the addresses? Is the entire memory written at virtually the same time, or are the addresses sequenced starting at #0?

Thanks,

Rad